Commit 063f7c82 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-dt-for-v4.15' of... 

Merge tag 'renesas-dt-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Pull "Renesas ARM Based SoC DT Updates for v4.15" from Simon Horman:

* r7s72100 (RZ/A1) Peach board
  - Add pin groups for SCIF2 serial debug interface and Ethernet
    This avoids relying on bootloader settings
  - Support control of LED1 using gpio-leds

* r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs
  - Add MSIOF[012] support and define aliases for spi[0123]

* r8a7743 (RZ/G1M) SoC
  - Add I2C and IIC core nodes

* r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven development platform
   - Enable SDHI1 SD controller supporting high-speed and SDR50 transfers
   - Add chosen node to allow correct selection of serial console
     and the kernel command line
   - Enable RTC support
   - Enable USB2.0 host support
     This includes enabling USB PHY and internal PCI

* r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven and
  r8a7745 (RZ/G1E) iW-RainboW-G22M-SM SoMs
   - Enable Add SPI NOR support
     This devices is used to boot up the system to the SoM DT

* r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM
  - Enable SDHI0 SD controller supporting high-speed transfers

* r8a7745 (RZ/G1E) iW-RainboW-G22D development platform
  - Add pnctl support for scif4
    This avoids reling on boot loader settings
  - Add EtherAVB support

* r8a7745 (RZ/G1E) iW-RainboW-G22M-SM SoM
  - Add basic SoM support
  - Enable MMCIF eMMC support
  - Enable RTC support
  - Enable SDHI1 SD controller supporting high-speed transfers

* r8a779[0-4] R-Car Gen2 SoCs
  - Add reset control properties
    Geert Uytterhoeven says:

    This patch series describes the reset topology on all R-Car Gen2 Socs,
    like was done before for R-Car Gen3 and RZ/G1.

    Resets usually match the corresponding module clocks.  Exceptions are:
      - The audio module has resets for the Serial Sound Interfaces only,
      - The display module has only a single reset for all DU channels, but
	adding reset properties for the display is postponed upon request
	from Laurent.

   - Convert to new CPG/MSSR bindings
     Geert Uytterhoven says:

     Currently Renesas R-Car Gen2 SoCs use the common clk-rcar-gen2,
     clk-mstp, and clk-div6 drivers, which depend on most clocks being
     described in DT.  Especially the module (MSTP) clocks are cumbersome
     and error prone, due to 3 arrays (clocks, clock-indices, and
     clock-output-names) to be kept in sync. In addition, the clk-mstp
     driver cannot be extended easily to also support module resets, which
     are provided by the same hardware module.

     Hence when developing support for R-Car Gen3 SoCs, another approach
     was chosen, which led to the CPG/MSSR driver core, and SoC-specific
     subdrivers (initially for R-Car Gen3, but later also for RZ/G1).

     This series converts the various R-Car Gen2 DTSes to migrate to the
     new CPG/MSSR drivers that were added in v4.13-rc1.

* r8a779[0,1,3,4] R-Car Gen2 SoCs
  - Stop grouping clocks under a "clocks" subnode
    Geert Uytterhoeven says:

    The current practice is to not group clocks under a "clocks" subnode,
    but just put them together with the other on-SoC devices.

    Hence this patch series implements this for the various R-Car Gen2
    DTSes that still need this (r8a7792.dtsi is OK).

* r8a7794 (E2) Alt board
  - Correct inverted sense of SD wip pins

* tag 'renesas-dt-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (48 commits)
  ARM: dts: r8a7743: Add MSIOF[012] support
  ARM: dts: r8a7745: Add MSIOF[012] support
  ARM: dts: iwg22d: Enable SDHI0 controller
  ARM: dts: iwg22m: Add SPI NOR support
  ARM: dts: r8a7745: Add QSPI support
  ARM: dts: iwg20m: Add SPI NOR support
  ARM: dts: r8a7743: Add QSPI support
  ARM: dts: iwg22m: Enable SDHI1 controller
  ARM: dts: r8a7745: Add SDHI controllers
  ARM: dts: r8a7794: Add reset control properties
  ARM: dts: r8a7793: Add reset control properties
  ARM: dts: r8a7792: Add reset control properties
  ARM: dts: r8a7791: Add reset control properties
  ARM: dts: r8a7790: Add reset control properties
  ARM: dts: r8a7743: Add IIC cores to dtsi
  ARM: dts: alt: use correct logic for SD WP pins
  ARM: dts: iwg20d-q7: Enable USB PHY
  ARM: dts: iwg20d-q7: Enable internal PCI
  ARM: dts: r8a7743: Link PCI USB devices to USB PHY
  ARM: dts: r8a7743: Add USB PHY DT support
  ...
parents c305cf33 7031a219

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -725,6 +725,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ 
	r8a7740-armadillo800eva.dtb \

	r8a7743-iwg20d-q7.dtb \

	r8a7743-sk-rzg1m.dtb \

	r8a7745-iwg22d-sodimm.dtb \

	r8a7745-sk-rzg1e.dtb \

	r8a7778-bockw.dtb \

	r8a7779-marzen.dtb \

arch/arm/boot/dts/r7s72100-gr-peach.dts

+21 −1
Original line number Diff line number Diff line
@@ -11,6 +11,8 @@ 


/dts-v1/;

#include "r7s72100.dtsi"

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>



/ {

	model = "GR-Peach";
@@ -28,7 +30,6 @@ 
	memory@20000000 {

		device_type = "memory";

		reg = <0x20000000 0x00a00000>;



	};



	lbsc {
@@ -51,6 +52,22 @@ 
			reg = <0x00600000 0x00200000>;

		};

	};



leds {

		status = "okay";

		compatible = "gpio-leds";



		led1 {

			gpios = <&port6 12 GPIO_ACTIVE_HIGH>;

		};

	};

};



&pinctrl {

	scif2_pins: serial2 {

		/* P6_2 as RxD2; P6_3 as TxD2 */

		pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;

	};

};



&extal_clk {
@@ -62,5 +79,8 @@ 
};



&scif2 {

	pinctrl-names = "default";

	pinctrl-0 = <&scif2_pins>;



	status = "okay";

};

arch/arm/boot/dts/r8a7743-iwg20d-q7.dts

+97 −0
Original line number Diff line number Diff line
@@ -19,9 +19,42 @@ 
		serial0 = &scif0;

		ethernet0 = &avb;

	};



	chosen {

		bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";

		stdout-path = "serial0:115200n8";

	};



	vcc_sdhi1: regulator-vcc-sdhi1 {

		compatible = "regulator-fixed";



		regulator-name = "SDHI1 Vcc";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;



		gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;

	};



	vccq_sdhi1: regulator-vccq-sdhi1 {

		compatible = "regulator-gpio";



		regulator-name = "SDHI1 VccQ";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <3300000>;



		gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;

		gpios-states = <1>;

		states = <3300000 1

			  1800000 0>;

	};

};



&pfc {

	i2c2_pins: i2c2 {

		groups = "i2c2";

		function = "i2c2";

	};



	scif0_pins: scif0 {

		groups = "scif0_data_d";

		function = "scif0";
@@ -31,6 +64,28 @@ 
		groups = "avb_mdio", "avb_gmii";

		function = "avb";

	};



	sdhi1_pins: sd1 {

		groups = "sdhi1_data4", "sdhi1_ctrl";

		function = "sdhi1";

		power-source = <3300>;

	};



	sdhi1_pins_uhs: sd1_uhs {

		groups = "sdhi1_data4", "sdhi1_ctrl";

		function = "sdhi1";

		power-source = <1800>;

	};



	usb0_pins: usb0 {

		groups = "usb0";

		function = "usb0";

	};



	usb1_pins: usb1 {

		groups = "usb1";

		function = "usb1";

	};

};



&scif0 {
@@ -54,3 +109,45 @@ 
		micrel,led-mode = <1>;

	};

};



&sdhi1 {

	pinctrl-0 = <&sdhi1_pins>;

	pinctrl-1 = <&sdhi1_pins_uhs>;

	pinctrl-names = "default", "state_uhs";



	vmmc-supply = <&vcc_sdhi1>;

	vqmmc-supply = <&vccq_sdhi1>;

	cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;

	wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;

	sd-uhs-sdr50;

	status = "okay";

};



&i2c2 {

	pinctrl-0 = <&i2c2_pins>;

	pinctrl-names = "default";



	status = "okay";

	clock-frequency = <400000>;



	rtc@68 {

		compatible = "ti,bq32000";

		reg = <0x68>;

	};

};



&pci0 {

	status = "okay";

	pinctrl-0 = <&usb0_pins>;

	pinctrl-names = "default";

};



&pci1 {

	status = "okay";

	pinctrl-0 = <&usb1_pins>;

	pinctrl-names = "default";

};



&usbphy {

	status = "okay";

};

arch/arm/boot/dts/r8a7743-iwg20m.dtsi

+43 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
 */



#include "r8a7743.dtsi"

#include <dt-bindings/gpio/gpio.h>



/ {

	compatible = "iwave,g20m", "renesas,r8a7743";
@@ -42,6 +43,17 @@ 
		groups = "mmc_data8_b", "mmc_ctrl";

		function = "mmc";

	};



	qspi_pins: qspi {

		groups = "qspi_ctrl", "qspi_data2";

		function = "qspi";

	};



	sdhi0_pins: sd0 {

		groups = "sdhi0_data4", "sdhi0_ctrl";

		function = "sdhi0";

		power-source = <3300>;

	};

};



&mmcif0 {
@@ -53,3 +65,34 @@ 
	non-removable;

	status = "okay";

};



&qspi {

	pinctrl-0 = <&qspi_pins>;

	pinctrl-names = "default";



	status = "okay";



	/* WARNING - This device contains the bootloader. Handle with care. */

	flash: flash@0 {

		#address-cells = <1>;

		#size-cells = <1>;

		compatible = "sst,sst25vf016b", "jedec,spi-nor";

		reg = <0>;

		spi-max-frequency = <50000000>;

		spi-tx-bus-width = <1>;

		spi-rx-bus-width = <1>;

		m25p,fast-read;

		spi-cpol;

		spi-cpha;

	};

};



&sdhi0 {

	pinctrl-0 = <&sdhi0_pins>;

	pinctrl-names = "default";



	vmmc-supply = <&reg_3p3v>;

	vqmmc-supply = <&reg_3p3v>;

	cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;

	status = "okay";

};

arch/arm/boot/dts/r8a7743.dtsi

+257 −0
Original line number Diff line number Diff line
@@ -25,6 +25,13 @@ 
		i2c3 = &i2c3;

		i2c4 = &i2c4;

		i2c5 = &i2c5;

		i2c6 = &iic0;

		i2c7 = &iic1;

		i2c8 = &iic3;

		spi0 = &qspi;

		spi1 = &msiof0;

		spi2 = &msiof1;

		spi3 = &msiof2;

	};



	cpus {
@@ -436,6 +443,58 @@ 
			status = "disabled";

		};



		iic0: i2c@e6500000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "renesas,iic-r8a7743",

				     "renesas,rcar-gen2-iic",

				     "renesas,rmobile-iic";

			reg = <0 0xe6500000 0 0x425>;

			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 318>;

			dmas = <&dmac0 0x61>, <&dmac0 0x62>,

			       <&dmac1 0x61>, <&dmac1 0x62>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 318>;

			status = "disabled";

		};



		iic1: i2c@e6510000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "renesas,iic-r8a7743",

				     "renesas,rcar-gen2-iic",

				     "renesas,rmobile-iic";

			reg = <0 0xe6510000 0 0x425>;

			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 323>;

			dmas = <&dmac0 0x65>, <&dmac0 0x66>,

			       <&dmac1 0x65>, <&dmac1 0x66>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 323>;

			status = "disabled";

		};



		iic3: i2c@e60b0000 {

			/* doesn't need pinmux */

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "renesas,iic-r8a7743",

				     "renesas,rcar-gen2-iic",

				     "renesas,rmobile-iic";

			reg = <0 0xe60b0000 0 0x425>;

			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 926>;

			dmas = <&dmac0 0x77>, <&dmac0 0x78>,

			       <&dmac1 0x77>, <&dmac1 0x78>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 926>;

			status = "disabled";

		};



		scifa0: serial@e6c40000 {

			compatible = "renesas,scifa-r8a7743",

				     "renesas,rcar-gen2-scifa", "renesas,scifa";
@@ -779,6 +838,204 @@ 
			max-frequency = <97500000>;

			status = "disabled";

		};



		qspi: spi@e6b10000 {

			compatible = "renesas,qspi-r8a7743", "renesas,qspi";

			reg = <0 0xe6b10000 0 0x2c>;

			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 917>;

			dmas = <&dmac0 0x17>, <&dmac0 0x18>,

			       <&dmac1 0x17>, <&dmac1 0x18>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			num-cs = <1>;

			#address-cells = <1>;

			#size-cells = <0>;

			resets = <&cpg 917>;

			status = "disabled";

		};



		msiof0: spi@e6e20000 {

			compatible = "renesas,msiof-r8a7743",

				     "renesas,rcar-gen2-msiof";

			reg = <0 0xe6e20000 0 0x0064>;

			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 000>;

			dmas = <&dmac0 0x51>, <&dmac0 0x52>,

			       <&dmac1 0x51>, <&dmac1 0x52>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			#address-cells = <1>;

			#size-cells = <0>;

			resets = <&cpg 000>;

			status = "disabled";

		};



		msiof1: spi@e6e10000 {

			compatible = "renesas,msiof-r8a7743",

				     "renesas,rcar-gen2-msiof";

			reg = <0 0xe6e10000 0 0x0064>;

			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 208>;

			dmas = <&dmac0 0x55>, <&dmac0 0x56>,

			       <&dmac1 0x55>, <&dmac1 0x56>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			#address-cells = <1>;

			#size-cells = <0>;

			resets = <&cpg 208>;

			status = "disabled";

		};



		msiof2: spi@e6e00000 {

			compatible = "renesas,msiof-r8a7743",

				     "renesas,rcar-gen2-msiof";

			reg = <0 0xe6e00000 0 0x0064>;

			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 205>;

			dmas = <&dmac0 0x41>, <&dmac0 0x42>,

			       <&dmac1 0x41>, <&dmac1 0x42>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			#address-cells = <1>;

			#size-cells = <0>;

			resets = <&cpg 205>;

			status = "disabled";

		};



		sdhi0: sd@ee100000 {

			compatible = "renesas,sdhi-r8a7743";

			reg = <0 0xee100000 0 0x328>;

			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 314>;

			dmas = <&dmac0 0xcd>, <&dmac0 0xce>,

			       <&dmac1 0xcd>, <&dmac1 0xce>;

			dma-names = "tx", "rx", "tx", "rx";

			max-frequency = <195000000>;

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 314>;

			status = "disabled";

		};



		sdhi1: sd@ee140000 {

			compatible = "renesas,sdhi-r8a7743";

			reg = <0 0xee140000 0 0x100>;

			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 312>;

			dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,

			       <&dmac1 0xc1>, <&dmac1 0xc2>;

			dma-names = "tx", "rx", "tx", "rx";

			max-frequency = <97500000>;

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 312>;

			status = "disabled";

		};



		sdhi2: sd@ee160000 {

			compatible = "renesas,sdhi-r8a7743";

			reg = <0 0xee160000 0 0x100>;

			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 311>;

			dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,

			       <&dmac1 0xd3>, <&dmac1 0xd4>;

			dma-names = "tx", "rx", "tx", "rx";

			max-frequency = <97500000>;

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 311>;

			status = "disabled";

		};



		usbphy: usb-phy@e6590100 {

			compatible = "renesas,usb-phy-r8a7743",

				     "renesas,rcar-gen2-usb-phy";

			reg = <0 0xe6590100 0 0x100>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&cpg CPG_MOD 704>;

			clock-names = "usbhs";

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 704>;

			status = "disabled";



			usb0: usb-channel@0 {

				reg = <0>;

				#phy-cells = <1>;

			};

			usb2: usb-channel@2 {

				reg = <2>;

				#phy-cells = <1>;

			};

		};



		pci0: pci@ee090000 {

			compatible = "renesas,pci-r8a7743",

				     "renesas,pci-rcar-gen2";

			device_type = "pci";

			reg = <0 0xee090000 0 0xc00>,

			      <0 0xee080000 0 0x1100>;

			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 703>;

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 703>;

			status = "disabled";



			bus-range = <0 0>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;

			interrupt-map-mask = <0xff00 0 0 0x7>;

			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH

					 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH

					 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;



			usb@1,0 {

				reg = <0x800 0 0 0 0>;

				phys = <&usb0 0>;

				phy-names = "usb";

			};



			usb@2,0 {

				reg = <0x1000 0 0 0 0>;

				phys = <&usb0 0>;

				phy-names = "usb";

			};

		};



		pci1: pci@ee0d0000 {

			compatible = "renesas,pci-r8a7743",

				     "renesas,pci-rcar-gen2";

			device_type = "pci";

			reg = <0 0xee0d0000 0 0xc00>,

			      <0 0xee0c0000 0 0x1100>;

			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 703>;

			power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;

			resets = <&cpg 703>;

			status = "disabled";



			bus-range = <1 1>;

			#address-cells = <3>;

			#size-cells = <2>;

			#interrupt-cells = <1>;

			ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;

			interrupt-map-mask = <0xff00 0 0 0x7>;

			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH

					 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH

					 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;



			usb@1,0 {

				reg = <0x10800 0 0 0 0>;

				phys = <&usb2 0>;

				phy-names = "usb";

			};



			usb@2,0 {

				reg = <0x11000 0 0 0 0>;

				phys = <&usb2 0>;

				phy-names = "usb";

			};

		};

	};



	/* External root clock */

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