clk: qcom: Add GDSC support for SDX55 GCC (063930ed) · Commits · 戴 / test

drivers/clk/qcom/Kconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -424,6 +424,7 @@ config SDM_LPASSCC_845

		config SDX_GCC_55
		tristate "SDX55 Global Clock Controller"
		select QCOM_GDSC
		help
		Support for the global clock controller on SDX55 devices.
		Say Y if you want to use peripheral devices such as UART,

+33 −0

Original line number	Diff line number	Diff line
		@@ -17,6 +17,7 @@
		#include "clk-pll.h"
		#include "clk-rcg.h"
		#include "clk-regmap.h"
		#include "gdsc.h"
		#include "reset.h"

		enum {
		@@ -1455,6 +1456,30 @@ static struct clk_branch gcc_xo_pcie_link_clk = {
		},
		};

		static struct gdsc usb30_gdsc = {
		.gdscr = 0x0b004,
		.pd = {
		.name = "usb30_gdsc",
		},
		.pwrsts = PWRSTS_OFF_ON,
		};

		static struct gdsc pcie_gdsc = {
		.gdscr = 0x37004,
		.pd = {
		.name = "pcie_gdsc",
		},
		.pwrsts = PWRSTS_OFF_ON,
		};

		static struct gdsc emac_gdsc = {
		.gdscr = 0x47004,
		.pd = {
		.name = "emac_gdsc",
		},
		.pwrsts = PWRSTS_OFF_ON,
		};

		static struct clk_regmap *gcc_sdx55_clocks[] = {
		[GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr,
		[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
		@@ -1560,6 +1585,12 @@ static const struct qcom_reset_map gcc_sdx55_resets[] = {
		[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 },
		};

		static struct gdsc *gcc_sdx55_gdscs[] = {
		[USB30_GDSC] = &usb30_gdsc,
		[PCIE_GDSC] = &pcie_gdsc,
		[EMAC_GDSC] = &emac_gdsc,
		};

		static const struct regmap_config gcc_sdx55_regmap_config = {
		.reg_bits = 32,
		.reg_stride = 4,
		@@ -1574,6 +1605,8 @@ static const struct qcom_cc_desc gcc_sdx55_desc = {
		.num_clks = ARRAY_SIZE(gcc_sdx55_clocks),
		.resets = gcc_sdx55_resets,
		.num_resets = ARRAY_SIZE(gcc_sdx55_resets),
		.gdscs = gcc_sdx55_gdscs,
		.num_gdscs = ARRAY_SIZE(gcc_sdx55_gdscs),
		};

		static const struct of_device_id gcc_sdx55_match_table[] = {