Commit 06030c4e authored by Lubomir Rintel's avatar Lubomir Rintel Committed by Stephen Boyd
Browse files

clk: mmp: frac: Do not lose last 4 digits of precision 



While calculating the output rate of a fractional divider clock, the
value is divided and multipled by 10000, discarding the least
significant digits -- presumably to fit the intermediate value within 32
bits.

The precision we're losing is, however, not insignificant for things like
I2S clock. Maybe also elsewhere, now that since commit ea56ad60 ("clk:
mmp2: Stop pretending PLL outputs are constant") the parent rates are more
precise and no longer rounded to 10000s.

Signed-off-by: default avatarLubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20200519224151.2074597-2-lkundrak@v3.sk


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 8f3d9f35

drivers/clk/mmp/clk-frac.c

+16 −8
Original line number Diff line number Diff line
@@ -28,13 +28,15 @@ static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate, 
		unsigned long *prate)

{

	struct mmp_clk_factor *factor = to_clk_factor(hw);

	unsigned long rate = 0, prev_rate;

	u64 rate = 0, prev_rate;

	int i;



	for (i = 0; i < factor->ftbl_cnt; i++) {

		prev_rate = rate;

		rate = (((*prate / 10000) * factor->ftbl[i].den) /

			(factor->ftbl[i].num * factor->masks->factor)) * 10000;

		rate = *prate;

		rate *= factor->ftbl[i].den;

		do_div(rate, factor->ftbl[i].num * factor->masks->factor);



		if (rate > drate)

			break;

	}
@@ -54,6 +56,7 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw, 
	struct mmp_clk_factor *factor = to_clk_factor(hw);

	struct mmp_clk_factor_masks *masks = factor->masks;

	unsigned int val, num, den;

	u64 rate;



	val = readl_relaxed(factor->base);
@@ -66,8 +69,11 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw, 
	if (!den)

		return 0;



	return (((parent_rate / 10000)  * den) /

			(num * factor->masks->factor)) * 10000;

	rate = parent_rate;

	rate *= den;

	do_div(rate, num * factor->masks->factor);



	return rate;

}



/* Configures new clock rate*/
@@ -78,12 +84,14 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate, 
	struct mmp_clk_factor_masks *masks = factor->masks;

	int i;

	unsigned long val;

	unsigned long rate = 0;

	unsigned long flags = 0;

	u64 rate = 0;



	for (i = 0; i < factor->ftbl_cnt; i++) {

		rate = (((prate / 10000) * factor->ftbl[i].den) /

			(factor->ftbl[i].num * factor->masks->factor)) * 10000;

		rate = prate;

		rate *= factor->ftbl[i].den;

		do_div(rate, factor->ftbl[i].num * factor->masks->factor);



		if (rate > drate)

			break;

	}

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