usb: dwc2: Move gadget settings into core_params (05ee799f) · Commits · 戴 / test

drivers/usb/dwc2/core.h

+24 −8

Original line number	Diff line number	Diff line
		@@ -418,6 +418,21 @@ enum dwc2_ep0_state {
		* needed.
		* 0 - No (default)
		* 1 - Yes
		* @g_dma: If true, enables dma usage on the device. This
		* setting is not auto-detected. It must be
		* explicitly enabled (default: false).
		* @g_rx_fifo_size: The periodic rx fifo size for the device, in
		* DWORDS from 16-32768 (default: 2048 if
		* possible, otherwise autodetect).
		* @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
		* DWORDS from 16-32768 (default: 1024 if
		* possible, otherwise autodetect).
		* @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
		* mode. Each value corresponds to one EP
		* starting from EP1 (max 15 values). Sizes are
		* in DWORDS with possible values from from
		* 16-32768 (default: 256, 256, 256, 256, 768,
		* 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
		*
		* The following parameters may be specified when starting the module. These
		* parameters define how the DWC_otg controller should be configured. A
		@@ -475,6 +490,15 @@ struct dwc2_core_params {
		int uframe_sched;
		int external_id_pin_ctl;
		int hibernation;

		/*
		* The following parameters are only set via device
		* properties and cannot be set directly in this structure.
		*/
		bool g_dma;
		u16 g_rx_fifo_size;
		u16 g_np_tx_fifo_size;
		u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
		};

		/**
		@@ -857,10 +881,6 @@ struct dwc2_hregs_backup {
		* @ep0_state: EP0 control transfers state
		* @test_mode: USB test mode requested by the host
		* @eps: The endpoints being supplied to the gadget framework
		* @g_using_dma: Indicate if dma usage is enabled
		* @g_rx_fifo_sz: Contains rx fifo size value
		* @g_np_g_tx_fifo_sz: Contains Non-Periodic tx fifo size value
		* @g_tx_fifo_sz: Contains tx fifo size value per endpoints
		*/
		struct dwc2_hsotg {
		struct device *dev;
		@@ -1008,10 +1028,6 @@ struct dwc2_hsotg {
		unsigned int connected:1;
		struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
		struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
		u32 g_using_dma;
		u32 g_rx_fifo_sz;
		u32 g_np_g_tx_fifo_sz;
		u32 g_tx_fifo_sz[MAX_EPS_CHANNELS];
		#endif /* CONFIG_USB_DWC2_PERIPHERAL \|\| CONFIG_USB_DWC2_DUAL_ROLE */
		};

drivers/usb/dwc2/gadget.c

+14 −79

Original line number	Diff line number	Diff line
		@@ -93,7 +93,7 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
		*/
		static inline bool using_dma(struct dwc2_hsotg *hsotg)
		{
		return hsotg->g_using_dma;
		return hsotg->params.g_dma;
		}

		/**
		@@ -190,15 +190,16 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
		unsigned int addr;
		int timeout;
		u32 val;
		u32 *txfsz = hsotg->params.g_tx_fifo_size;

		/* Reset fifo map if not correctly cleared during previous session */
		WARN_ON(hsotg->fifo_map);
		hsotg->fifo_map = 0;

		/* set RX/NPTX FIFO sizes */
		dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
		dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) \|
		(hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
		dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ);
		dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) \|
		(hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT),
		hsotg->regs + GNPTXFSIZ);

		/*
		@@ -209,7 +210,7 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
		*/

		/* start at the end of the GNPTXFSIZ, rounded up */
		addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
		addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;

		/*
		* Configure fifos sizes from provided configuration and assign
		@@ -217,15 +218,16 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
		* given endpoint.
		*/
		for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
		if (!hsotg->g_tx_fifo_sz[ep])
		if (!txfsz[ep])
		continue;
		val = addr;
		val \|= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
		WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
		val \|= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
		WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem,
		"insufficient fifo memory");
		addr += hsotg->g_tx_fifo_sz[ep];
		addr += txfsz[ep];

		dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
		val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep));
		}

		/*
		@@ -3800,51 +3802,6 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
		#endif
		}

		#ifdef CONFIG_OF
		static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg)
		{
		struct device_node *np = hsotg->dev->of_node;
		u32 len = 0;
		u32 i = 0;

		/* Enable dma if requested in device tree */
		hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");

		/*
		* Register TX periodic fifo size per endpoint.
		* EP0 is excluded since it has no fifo configuration.
		*/
		if (!of_find_property(np, "g-tx-fifo-size", &len))
		goto rx_fifo;

		len /= sizeof(u32);

		/* Read tx fifo sizes other than ep0 */
		if (of_property_read_u32_array(np, "g-tx-fifo-size",
		&hsotg->g_tx_fifo_sz[1], len))
		goto rx_fifo;

		/* Add ep0 */
		len++;

		/* Make remaining TX fifos unavailable */
		if (len < MAX_EPS_CHANNELS) {
		for (i = len; i < MAX_EPS_CHANNELS; i++)
		hsotg->g_tx_fifo_sz[i] = 0;
		}

		rx_fifo:
		/* Register RX fifo size */
		of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);

		/* Register NPTX fifo size */
		of_property_read_u32(np, "g-np-tx-fifo-size",
		&hsotg->g_np_g_tx_fifo_sz);
		}
		#else
		static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
		#endif

		/**
		* dwc2_gadget_init - init function for gadget
		* @dwc2: The data structure for the DWC2 driver.
		@@ -3855,33 +3812,11 @@ int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
		struct device *dev = hsotg->dev;
		int epnum;
		int ret;
		int i;
		u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;

		/* Initialize to legacy fifo configuration values */
		hsotg->g_rx_fifo_sz = 2048;
		hsotg->g_np_g_tx_fifo_sz = 1024;
		memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
		/* Device tree specific probe */
		dwc2_hsotg_of_probe(hsotg);

		/* Check against largest possible value. */
		if (hsotg->g_np_g_tx_fifo_sz >
		hsotg->hw_params.dev_nperio_tx_fifo_size) {
		dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n",
		hsotg->g_np_g_tx_fifo_sz,
		hsotg->hw_params.dev_nperio_tx_fifo_size);
		hsotg->g_np_g_tx_fifo_sz =
		hsotg->hw_params.dev_nperio_tx_fifo_size;
		}

		/* Dump fifo information */
		dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
		hsotg->g_np_g_tx_fifo_sz);
		dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
		for (i = 0; i < MAX_EPS_CHANNELS; i++)
		dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
		hsotg->g_tx_fifo_sz[i]);
		hsotg->params.g_np_tx_fifo_size);
		dev_dbg(dev, "RXFIFO size: %d\n", hsotg->params.g_rx_fifo_size);

		hsotg->gadget.max_speed = USB_SPEED_HIGH;
		hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;

drivers/usb/dwc2/params.c

+258 −4

Original line number	Diff line number	Diff line
		@@ -249,6 +249,187 @@ const struct of_device_id dwc2_of_match_table[] = {
		};
		MODULE_DEVICE_TABLE(of, dwc2_of_match_table);

		static void dwc2_get_device_property(struct dwc2_hsotg *hsotg,
		char property, u8 size, u64 value)
		{
		u8 val8;
		u16 val16;
		u32 val32;

		switch (size) {
		case 0:
		*value = device_property_read_bool(hsotg->dev, property);
		break;
		case 1:
		if (device_property_read_u8(hsotg->dev, property, &val8))
		return;

		*value = val8;
		break;
		case 2:
		if (device_property_read_u16(hsotg->dev, property, &val16))
		return;

		*value = val16;
		break;
		case 4:
		if (device_property_read_u32(hsotg->dev, property, &val32))
		return;

		*value = val32;
		break;
		case 8:
		if (device_property_read_u64(hsotg->dev, property, value))
		return;

		break;
		default:
		/*
		* The size is checked by the only function that calls
		* this so this should never happen.
		*/
		WARN_ON(1);
		return;
		}
		}

		static void dwc2_set_core_param(void *param, u8 size, u64 value)
		{
		switch (size) {
		case 0:
		((bool )param) = !!value;
		break;
		case 1:
		((u8 )param) = (u8)value;
		break;
		case 2:
		((u16 )param) = (u16)value;
		break;
		case 4:
		((u32 )param) = (u32)value;
		break;
		case 8:
		((u64 )param) = (u64)value;
		break;
		default:
		/*
		* The size is checked by the only function that calls
		* this so this should never happen.
		*/
		WARN_ON(1);
		return;
		}
		}

		/**
		* dwc2_set_param() - Set a core parameter
		*
		* @hsotg: Programming view of the DWC_otg controller
		* @param: Pointer to the parameter to set
		* @lookup: True if the property should be looked up
		* @property: The device property to read
		* @legacy: The param value to set if @property is not available. This
		* will typically be the legacy value set in the static
		* params structure.
		* @def: The default value
		* @min: The minimum value
		* @max: The maximum value
		* @size: The size of the core parameter in bytes, or 0 for bool.
		*
		* This function looks up @property and sets the @param to that value.
		* If the property doesn't exist it uses the passed-in @value. It will
		* verify that the value falls between @min and @max. If it doesn't,
		* it will output an error and set the parameter to either @def or,
		* failing that, to @min.
		*
		* The @size is used to write to @param and to query the device
		* properties so that this same function can be used with different
		* types of parameters.
		*/
		static void dwc2_set_param(struct dwc2_hsotg hsotg, void param,
		bool lookup, char *property, u64 legacy,
		u64 def, u64 min, u64 max, u8 size)
		{
		u64 sizemax;
		u64 value;

		if (WARN_ON(!hsotg \|\| !param \|\| !property))
		return;

		if (WARN((size > 8) \|\| ((size & (size - 1)) != 0),
		"Invalid size %d for %s\n", size, property))
		return;

		dev_vdbg(hsotg->dev, "%s: Setting %s: legacy=%llu, def=%llu, min=%llu, max=%llu, size=%d\n",
		__func__, property, legacy, def, min, max, size);

		sizemax = (1ULL << (size * 8)) - 1;
		value = legacy;

		/* Override legacy settings. */
		if (lookup)
		dwc2_get_device_property(hsotg, property, size, &value);

		/*
		* While the value is not valid, try setting it to the default
		* value, and failing that, set it to the minimum.
		*/
		while ((value < min) \|\| (value > max)) {
		/* Print an error unless the value is set to auto. */
		if (value != sizemax)
		dev_err(hsotg->dev, "Invalid value %llu for param %s\n",
		value, property);

		/*
		* If we are already the default, just set it to the
		* minimum.
		*/
		if (value == def) {
		dev_vdbg(hsotg->dev, "%s: setting value to min=%llu\n",
		__func__, min);
		value = min;
		break;
		}

		/* Try the default value */
		dev_vdbg(hsotg->dev, "%s: setting value to default=%llu\n",
		__func__, def);
		value = def;
		}

		dev_dbg(hsotg->dev, "Setting %s to %llu\n", property, value);
		dwc2_set_core_param(param, size, value);
		}

		/**
		* dwc2_set_param_u16() - Set a u16 parameter
		*
		* See dwc2_set_param().
		*/
		static void dwc2_set_param_u16(struct dwc2_hsotg hsotg, u16 param,
		bool lookup, char *property, u16 legacy,
		u16 def, u16 min, u16 max)
		{
		dwc2_set_param(hsotg, param, lookup, property,
		legacy, def, min, max, 2);
		}

		/**
		* dwc2_set_param_bool() - Set a bool parameter
		*
		* See dwc2_set_param().
		*
		* Note: there is no 'legacy' argument here because there is no legacy
		* source of bool params.
		*/
		static void dwc2_set_param_bool(struct dwc2_hsotg hsotg, bool param,
		bool lookup, char *property,
		bool def, bool min, bool max)
		{
		dwc2_set_param(hsotg, param, lookup, property,
		def, def, min, max, 0);
		}

		#define DWC2_OUT_OF_BOUNDS(a, b, c) ((a) < (b) \|\| (a) > (c))

		/* Parameter access functions */
		@@ -897,14 +1078,52 @@ static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
		hsotg->params.hibernation = val;
		}

		/*
		* This function is called during module intialization to pass module parameters
		* for the DWC_otg core.
		static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
		{
		int i;
		int num;
		char *property = "g-tx-fifo-size";
		struct dwc2_core_params *p = &hsotg->params;

		memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));

		/* Read tx fifo sizes */
		num = device_property_read_u32_array(hsotg->dev, property, NULL, 0);

		if (num > 0) {
		device_property_read_u32_array(hsotg->dev, property,
		&p->g_tx_fifo_size[1],
		num);
		} else {
		u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;

		memcpy(&p->g_tx_fifo_size[1],
		p_tx_fifo,
		sizeof(p_tx_fifo));

		num = ARRAY_SIZE(p_tx_fifo);
		}

		for (i = 0; i < num; i++) {
		if ((i + 1) >= ARRAY_SIZE(p->g_tx_fifo_size))
		break;

		dev_dbg(hsotg->dev, "Setting %s[%d] to %d\n",
		property, i + 1, p->g_tx_fifo_size[i + 1]);
		}
		}

		/**
		* dwc2_set_parameters() - Set all core parameters.
		*
		* @hsotg: Programming view of the DWC_otg controller
		* @params: The parameters to set
		*/
		static void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
		const struct dwc2_core_params *params)
		{
		dev_dbg(hsotg->dev, "%s()\n", __func__);
		struct dwc2_hw_params *hw = &hsotg->hw_params;
		struct dwc2_core_params *p = &hsotg->params;

		dwc2_set_param_otg_cap(hsotg, params->otg_cap);
		dwc2_set_param_dma_enable(hsotg, params->dma_enable);
		@@ -944,6 +1163,41 @@ static void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
		dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
		dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
		dwc2_set_param_hibernation(hsotg, params->hibernation);

		/*
		* Set devicetree-only parameters. These parameters do not
		* take any values from @params.
		*/
		if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) \|\|
		(hsotg->dr_mode == USB_DR_MODE_OTG)) {
		dev_dbg(hsotg->dev, "Setting peripheral device properties\n");

		dwc2_set_param_bool(hsotg, &p->g_dma, true, "g-use-dma",
		false, false,
		hsotg->hw_params.arch !=
		GHWCFG2_SLAVE_ONLY_ARCH);

		/*
		* The values for g_rx_fifo_size (2048) and
		* g_np_tx_fifo_size (1024) come from the legacy s3c
		* gadget driver. These defaults have been hard-coded
		* for some time so many platforms depend on these
		* values. Leave them as defaults for now and only
		* auto-detect if the hardware does not support the
		* default.
		*/
		dwc2_set_param_u16(hsotg, &p->g_rx_fifo_size,
		true, "g-rx-fifo-size", 2048,
		hw->rx_fifo_size,
		16, hw->rx_fifo_size);

		dwc2_set_param_u16(hsotg, &p->g_np_tx_fifo_size,
		true, "g-np-tx-fifo-size", 1024,
		hw->dev_nperio_tx_fifo_size,
		16, hw->dev_nperio_tx_fifo_size);

		dwc2_set_param_tx_fifo_sizes(hsotg);
		}
		}

		/*

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