drm/i915/tgl: Fix TC-cold block/unblock sequence (05e31dd7) · Commits · 戴 / test

The command register is the PCODE MBOX low register not the high one as described by the spec. This left the system with the TC-cold power state being blocked all the time. Fix things by using the correct register. Also to make sure we retry a request for at least 600usec, when the PCODE MBOX command itself succeeded, but the TC-cold block command failed, sleep for 1msec unconditionally after any fail. The change was tested with JTAG register read of the HW/FW's actual TC-cold state, which reported the expected states after this change. Tested-by:

Nivedita Swaminathan <nivedita.swaminathan@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:

Imre Deak <imre.deak@intel.com> Reviewed-by:

José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200805150056.24248-1-imre.deak@intel.com Signed-off-by:

Rodrigo Vivi <rodrigo.vivi@intel.com>

drivers/gpu/drm/i915/display/intel_display_power.c

+5 −5

Original line number	Diff line number	Diff line
		@@ -3927,12 +3927,13 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
		int ret;

		while (1) {
		u32 low_val = 0, high_val;
		u32 low_val;
		u32 high_val = 0;

		if (block)
		high_val = TGL_PCODE_EXIT_TCCOLD_DATA_H_BLOCK_REQ;
		low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ;
		else
		high_val = TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ;
		low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ;

		/*
		* Spec states that we should timeout the request after 200us
		@@ -3951,7 +3952,6 @@ tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
		if (++tries == 3)
		break;

		if (ret == -EAGAIN)
		msleep(1);
		}

drivers/gpu/drm/i915/i915_reg.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -9226,8 +9226,8 @@ enum {
		#define DISPLAY_IPS_CONTROL 0x19
		#define TGL_PCODE_TCCOLD 0x26
		#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
		#define TGL_PCODE_EXIT_TCCOLD_DATA_H_BLOCK_REQ 0
		#define TGL_PCODE_EXIT_TCCOLD_DATA_H_UNBLOCK_REQ REG_BIT(0)
		#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
		#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
		/* See also IPS_CTL */
		#define IPS_PCODE_CONTROL (1 << 30)
		#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A

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