Commit 05c6cfb9 authored by Alexey Kardashevskiy's avatar Alexey Kardashevskiy Committed by Michael Ellerman
Browse files

powerpc/iommu/powernv: Release replaced TCE 



At the moment writing new TCE value to the IOMMU table fails with EBUSY
if there is a valid entry already. However PAPR specification allows
the guest to write new TCE value without clearing it first.

Another problem this patch is addressing is the use of pool locks for
external IOMMU users such as VFIO. The pool locks are to protect
DMA page allocator rather than entries and since the host kernel does
not control what pages are in use, there is no point in pool locks and
exchange()+put_page(oldtce) is sufficient to avoid possible races.

This adds an exchange() callback to iommu_table_ops which does the same
thing as set() plus it returns replaced TCE and DMA direction so
the caller can release the pages afterwards. The exchange() receives
a physical address unlike set() which receives linear mapping address;
and returns a physical address as the clear() does.

This implements exchange() for P5IOC2/IODA/IODA2. This adds a requirement
for a platform to have exchange() implemented in order to support VFIO.

This replaces iommu_tce_build() and iommu_clear_tce() with
a single iommu_tce_xchg().

This makes sure that TCE permission bits are not set in TCE passed to
IOMMU API as those are to be calculated by platform code from
DMA direction.

This moves SetPageDirty() to the IOMMU code to make it work for both
VFIO ioctl interface in in-kernel TCE acceleration (when it becomes
available later).

Signed-off-by: default avatarAlexey Kardashevskiy <aik@ozlabs.ru>
[aw: for the vfio related changes]
Acked-by: default avatarAlex Williamson <alex.williamson@redhat.com>
Reviewed-by: default avatarDavid Gibson <david@gibson.dropbear.id.au>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent c5bb44ed

arch/powerpc/include/asm/iommu.h

+18 −4
Original line number Diff line number Diff line
@@ -45,13 +45,29 @@ extern int iommu_is_off; 
extern int iommu_force_on;



struct iommu_table_ops {

	/*

	 * When called with direction==DMA_NONE, it is equal to clear().

	 * uaddr is a linear map address.

	 */

	int (*set)(struct iommu_table *tbl,

			long index, long npages,

			unsigned long uaddr,

			enum dma_data_direction direction,

			struct dma_attrs *attrs);

#ifdef CONFIG_IOMMU_API

	/*

	 * Exchanges existing TCE with new TCE plus direction bits;

	 * returns old TCE and DMA direction mask.

	 * @tce is a physical address.

	 */

	int (*exchange)(struct iommu_table *tbl,

			long index,

			unsigned long *hpa,

			enum dma_data_direction *direction);

#endif

	void (*clear)(struct iommu_table *tbl,

			long index, long npages);

	/* get() returns a physical address */

	unsigned long (*get)(struct iommu_table *tbl, long index);

	void (*flush)(struct iommu_table *tbl);

};
@@ -153,6 +169,8 @@ extern void iommu_register_group(struct iommu_table_group *table_group, 
extern int iommu_add_device(struct device *dev);

extern void iommu_del_device(struct device *dev);

extern int __init tce_iommu_bus_notifier_init(void);

extern long iommu_tce_xchg(struct iommu_table *tbl, unsigned long entry,

		unsigned long *hpa, enum dma_data_direction *direction);

#else

static inline void iommu_register_group(struct iommu_table_group *table_group,

					int pci_domain_number,
@@ -225,10 +243,6 @@ extern int iommu_tce_clear_param_check(struct iommu_table *tbl, 
		unsigned long npages);

extern int iommu_tce_put_param_check(struct iommu_table *tbl,

		unsigned long ioba, unsigned long tce);

extern int iommu_tce_build(struct iommu_table *tbl, unsigned long entry,

		unsigned long hwaddr, enum dma_data_direction direction);

extern unsigned long iommu_clear_tce(struct iommu_table *tbl,

		unsigned long entry);



extern void iommu_flush_tce(struct iommu_table *tbl);

extern int iommu_take_ownership(struct iommu_table *tbl);

arch/powerpc/kernel/iommu.c

+19 −40
Original line number Diff line number Diff line
@@ -965,10 +965,7 @@ EXPORT_SYMBOL_GPL(iommu_tce_clear_param_check); 
int iommu_tce_put_param_check(struct iommu_table *tbl,

		unsigned long ioba, unsigned long tce)

{

	if (!(tce & (TCE_PCI_WRITE | TCE_PCI_READ)))

		return -EINVAL;



	if (tce & ~(IOMMU_PAGE_MASK(tbl) | TCE_PCI_WRITE | TCE_PCI_READ))

	if (tce & ~IOMMU_PAGE_MASK(tbl))

		return -EINVAL;



	if (ioba & ~IOMMU_PAGE_MASK(tbl))
@@ -985,44 +982,16 @@ int iommu_tce_put_param_check(struct iommu_table *tbl, 
}

EXPORT_SYMBOL_GPL(iommu_tce_put_param_check);



unsigned long iommu_clear_tce(struct iommu_table *tbl, unsigned long entry)

long iommu_tce_xchg(struct iommu_table *tbl, unsigned long entry,

		unsigned long *hpa, enum dma_data_direction *direction)

{

	unsigned long oldtce;

	struct iommu_pool *pool = get_pool(tbl, entry);



	spin_lock(&(pool->lock));

	long ret;



	oldtce = tbl->it_ops->get(tbl, entry);

	if (oldtce & (TCE_PCI_WRITE | TCE_PCI_READ))

		tbl->it_ops->clear(tbl, entry, 1);

	else

		oldtce = 0;

	ret = tbl->it_ops->exchange(tbl, entry, hpa, direction);



	spin_unlock(&(pool->lock));



	return oldtce;

}

EXPORT_SYMBOL_GPL(iommu_clear_tce);



/*

 * hwaddr is a kernel virtual address here (0xc... bazillion),

 * tce_build converts it to a physical address.

 */

int iommu_tce_build(struct iommu_table *tbl, unsigned long entry,

		unsigned long hwaddr, enum dma_data_direction direction)

{

	int ret = -EBUSY;

	unsigned long oldtce;

	struct iommu_pool *pool = get_pool(tbl, entry);



	spin_lock(&(pool->lock));



	oldtce = tbl->it_ops->get(tbl, entry);

	/* Add new entry if it is not busy */

	if (!(oldtce & (TCE_PCI_WRITE | TCE_PCI_READ)))

		ret = tbl->it_ops->set(tbl, entry, 1, hwaddr, direction, NULL);



	spin_unlock(&(pool->lock));

	if (!ret && ((*direction == DMA_FROM_DEVICE) ||

			(*direction == DMA_BIDIRECTIONAL)))

		SetPageDirty(pfn_to_page(*hpa >> PAGE_SHIFT));



	/* if (unlikely(ret))

		pr_err("iommu_tce: %s failed on hwaddr=%lx ioba=%lx kva=%lx ret=%d\n",
@@ -1031,13 +1000,23 @@ int iommu_tce_build(struct iommu_table *tbl, unsigned long entry, 


	return ret;

}

EXPORT_SYMBOL_GPL(iommu_tce_build);

EXPORT_SYMBOL_GPL(iommu_tce_xchg);



int iommu_take_ownership(struct iommu_table *tbl)

{

	unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;

	int ret = 0;



	/*

	 * VFIO does not control TCE entries allocation and the guest

	 * can write new TCEs on top of existing ones so iommu_tce_build()

	 * must be able to release old pages. This functionality

	 * requires exchange() callback defined so if it is not

	 * implemented, we disallow taking ownership over the table.

	 */

	if (!tbl->it_ops->exchange)

		return -EINVAL;



	spin_lock_irqsave(&tbl->large_pool.lock, flags);

	for (i = 0; i < tbl->nr_pools; i++)

		spin_lock(&tbl->pools[i].lock);

arch/powerpc/platforms/powernv/pci-ioda.c

+34 −0
Original line number Diff line number Diff line
@@ -1738,6 +1738,20 @@ static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, 
	return ret;

}



#ifdef CONFIG_IOMMU_API

static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index,

		unsigned long *hpa, enum dma_data_direction *direction)

{

	long ret = pnv_tce_xchg(tbl, index, hpa, direction);



	if (!ret && (tbl->it_type &

			(TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))

		pnv_pci_ioda1_tce_invalidate(tbl, index, 1, false);



	return ret;

}

#endif



static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index,

		long npages)

{
@@ -1749,6 +1763,9 @@ static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, 


static struct iommu_table_ops pnv_ioda1_iommu_ops = {

	.set = pnv_ioda1_tce_build,

#ifdef CONFIG_IOMMU_API

	.exchange = pnv_ioda1_tce_xchg,

#endif

	.clear = pnv_ioda1_tce_free,

	.get = pnv_tce_get,

};
@@ -1824,6 +1841,20 @@ static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, 
	return ret;

}



#ifdef CONFIG_IOMMU_API

static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index,

		unsigned long *hpa, enum dma_data_direction *direction)

{

	long ret = pnv_tce_xchg(tbl, index, hpa, direction);



	if (!ret && (tbl->it_type &

			(TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE)))

		pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false);



	return ret;

}

#endif



static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index,

		long npages)

{
@@ -1835,6 +1866,9 @@ static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, 


static struct iommu_table_ops pnv_ioda2_iommu_ops = {

	.set = pnv_ioda2_tce_build,

#ifdef CONFIG_IOMMU_API

	.exchange = pnv_ioda2_tce_xchg,

#endif

	.clear = pnv_ioda2_tce_free,

	.get = pnv_tce_get,

};

arch/powerpc/platforms/powernv/pci-p5ioc2.c

+3 −0
Original line number Diff line number Diff line
@@ -85,6 +85,9 @@ static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { } 


static struct iommu_table_ops pnv_p5ioc2_iommu_ops = {

	.set = pnv_tce_build,

#ifdef CONFIG_IOMMU_API

	.exchange = pnv_tce_xchg,

#endif

	.clear = pnv_tce_free,

	.get = pnv_tce_get,

};

arch/powerpc/platforms/powernv/pci.c

+18 −0
Original line number Diff line number Diff line
@@ -598,6 +598,24 @@ int pnv_tce_build(struct iommu_table *tbl, long index, long npages, 
	return 0;

}



#ifdef CONFIG_IOMMU_API

int pnv_tce_xchg(struct iommu_table *tbl, long index,

		unsigned long *hpa, enum dma_data_direction *direction)

{

	u64 proto_tce = iommu_direction_to_tce_perm(*direction);

	unsigned long newtce = *hpa | proto_tce, oldtce;

	unsigned long idx = index - tbl->it_offset;



	BUG_ON(*hpa & ~IOMMU_PAGE_MASK(tbl));



	oldtce = xchg(pnv_tce(tbl, idx), cpu_to_be64(newtce));

	*hpa = be64_to_cpu(oldtce) & ~(TCE_PCI_READ | TCE_PCI_WRITE);

	*direction = iommu_tce_direction(oldtce);



	return 0;

}

#endif



void pnv_tce_free(struct iommu_table *tbl, long index, long npages)

{

	long i;

CRA Git | Maintained and supported by SUSTech CRA and CCSE