Commit 05c0a8a9 authored by Andrew Jeffery's avatar Andrew Jeffery Committed by Linus Walleij
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pinctrl: aspeed-g6: Add bias controls for 1.8V GPIO banks



These were skipped in the original patches adding pinconf support for
the AST2600.

Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Cc: Johnny Huang <johnny_huang@aspeedtech.com>
Link: https://lore.kernel.org/r/20200910025631.2996342-4-andrew@aj.id.au


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 1d6db5ae
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+17 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@

#define SCU400		0x400 /* Multi-function Pin Control #1  */
#define SCU404		0x404 /* Multi-function Pin Control #2  */
#define SCU40C		0x40C /* Multi-function Pin Control #3  */
#define SCU410		0x410 /* Multi-function Pin Control #4  */
#define SCU414		0x414 /* Multi-function Pin Control #5  */
#define SCU418		0x418 /* Multi-function Pin Control #6  */
@@ -2591,6 +2592,22 @@ static struct aspeed_pin_config aspeed_g6_configs[] = {
	/* MAC4 */
	{ PIN_CONFIG_POWER_SOURCE,   { F24, B24 }, SCU458, BIT_MASK(5)},
	{ PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},

	/* GPIO18E */
	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, Y4, SCU40C, 4),
	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE,   Y1, Y4, SCU40C, 4),
	/* GPIO18D */
	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AB4, AC5, SCU40C, 3),
	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE,   AB4, AC5, SCU40C, 3),
	/* GPIO18C */
	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E4, E1, SCU40C, 2),
	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE,   E4, E1, SCU40C, 2),
	/* GPIO18B */
	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D3, SCU40C, 1),
	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE,   B2, D3, SCU40C, 1),
	/* GPIO18A */
	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C6, A2, SCU40C, 0),
	ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE,   C6, A2, SCU40C, 0),
};

/**