Commit 05abb126 authored by Alexander Duyck's avatar Alexander Duyck Committed by David S. Miller
Browse files

ixgbe: consolidate all setting of MRQC into one function 



This change simplifies the configuration of MRQC by consolidating the
setting of it into one function. As such the register is no longer set in
multiple places which should make any future changes easier to work with.
In addition we can combine RSS related register writes into the call since
enabling all of those bits without enabling RSS itself in MRQC should have
no effect.

Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 43e69bf0

drivers/net/ixgbe/ixgbe_main.c

+43 −57
Original line number Diff line number Diff line
@@ -2545,14 +2545,40 @@ static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, 
	IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);

}



static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)

static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)

{

	u32 mrqc = 0;

	struct ixgbe_hw *hw = &adapter->hw;

	static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,

	                  0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,

	                  0x6A3E67EA, 0x14364D17, 0x3BED200D};

	u32 mrqc = 0, reta = 0;

	u32 rxcsum;

	int i, j;

	int mask;



	if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))

		return mrqc;

	/* Fill out hash function seeds */

	for (i = 0; i < 10; i++)

		IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);



	/* Fill out redirection table */

	for (i = 0, j = 0; i < 128; i++, j++) {

		if (j == adapter->ring_feature[RING_F_RSS].indices)

			j = 0;

		/* reta = 4-byte sliding window of

		 * 0x00..(indices-1)(indices-1)00..etc. */

		reta = (reta << 8) | (j * 0x11);

		if ((i & 3) == 3)

			IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);

	}



	/* Disable indicating checksum in descriptor, enables RSS hash */

	rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);

	rxcsum |= IXGBE_RXCSUM_PCSD;

	IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);



	if (adapter->hw.mac.type == ixgbe_mac_82598EB)

		mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;

	else

		mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED

#ifdef CONFIG_IXGBE_DCB

					 | IXGBE_FLAG_DCB_ENABLED
@@ -2576,7 +2602,13 @@ static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) 
		break;

	}



	return mrqc;

	/* Perform hash on these packet types */

	mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4

	      | IXGBE_MRQC_RSS_FIELD_IPV4_TCP

	      | IXGBE_MRQC_RSS_FIELD_IPV6

	      | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;



	IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);

}



/**
@@ -2637,12 +2669,8 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 
	struct net_device *netdev = adapter->netdev;

	int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;

	int i, j;

	u32 rdlen, rxctrl, rxcsum;

	static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,

	                  0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,

	                  0x6A3E67EA, 0x14364D17, 0x3BED200D};

	u32 rdlen, rxctrl;

	u32 fctrl, hlreg0;

	u32 reta = 0, mrqc = 0;

	u32 rdrxctl;

	int rx_buf_len;
@@ -2774,33 +2802,7 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 
	}



	/* Program MRQC for the distribution of queues */

	mrqc = ixgbe_setup_mrqc(adapter);



	if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {

		/* Fill out redirection table */

		for (i = 0, j = 0; i < 128; i++, j++) {

			if (j == adapter->ring_feature[RING_F_RSS].indices)

				j = 0;

			/* reta = 4-byte sliding window of

			 * 0x00..(indices-1)(indices-1)00..etc. */

			reta = (reta << 8) | (j * 0x11);

			if ((i & 3) == 3)

				IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);

		}



		/* Fill out hash function seeds */

		for (i = 0; i < 10; i++)

			IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);



		if (hw->mac.type == ixgbe_mac_82598EB)

			mrqc |= IXGBE_MRQC_RSSEN;

		    /* Perform hash on these packet types */

		mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4

		      | IXGBE_MRQC_RSS_FIELD_IPV4_TCP

		      | IXGBE_MRQC_RSS_FIELD_IPV6

		      | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;

	}

	IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);

	ixgbe_setup_mrqc(adapter);



	if (adapter->num_vfs) {

		u32 reg;
@@ -2816,22 +2818,6 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) 
		IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, reg);

	}



	rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);



	if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||

	    adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {

		/* Disable indicating checksum in descriptor, enables

		 * RSS hash */

		rxcsum |= IXGBE_RXCSUM_PCSD;

	}

	if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {

		/* Enable IPv4 payload checksum for UDP fragments

		 * if PCSD is not set */

		rxcsum |= IXGBE_RXCSUM_IPPCSE;

	}



	IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);



	if (hw->mac.type == ixgbe_mac_82599EB) {

		rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);

		rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;

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