Commit 05ab303b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.13-rc7-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC fixes from Vineet Gupta:

 - PAE40 related updates

 - SLC errata for region ops

 - intc line masking by default

* tag 'arc-4.13-rc7-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  arc: Mask individual IRQ lines during core INTC init
  ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoC
  ARCv2: PAE40: Explicitly set MSB counterpart of SLC region ops addresses
  ARC: dma: implement dma_unmap_page and sg variant
  ARCv2: SLC: Make sure busy bit is set properly for region ops
  ARC: [plat-sim] Include this platform unconditionally
  ARC: [plat-axs10x]: prepare dts files for enabling PAE40 on axs103
  ARC: defconfig: Cleanup from old Kconfig options
parents 0b3baec8 a8ec3ee8

arch/arc/Kconfig

+0 −1
Original line number Diff line number Diff line
@@ -96,7 +96,6 @@ menu "ARC Architecture Configuration" 


menu "ARC Platform/SoC/Board"



source "arch/arc/plat-sim/Kconfig"

source "arch/arc/plat-tb10x/Kconfig"

source "arch/arc/plat-axs10x/Kconfig"

#New platform adds here

arch/arc/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -107,7 +107,7 @@ core-y += arch/arc/ 
# w/o this dtb won't embed into kernel binary

core-y		+= arch/arc/boot/dts/



core-$(CONFIG_ARC_PLAT_SIM)	+= arch/arc/plat-sim/

core-y				+= arch/arc/plat-sim/

core-$(CONFIG_ARC_PLAT_TB10X)	+= arch/arc/plat-tb10x/

core-$(CONFIG_ARC_PLAT_AXS10X)	+= arch/arc/plat-axs10x/

core-$(CONFIG_ARC_PLAT_EZNPS)	+= arch/arc/plat-eznps/

arch/arc/boot/dts/axc001.dtsi

+9 −11
Original line number Diff line number Diff line
@@ -15,15 +15,15 @@ 


/ {

	compatible = "snps,arc";

	#address-cells = <1>;

	#size-cells = <1>;

	#address-cells = <2>;

	#size-cells = <2>;



	cpu_card {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;



		ranges = <0x00000000 0xf0000000 0x10000000>;

		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;



		core_clk: core_clk {

			#clock-cells = <0>;
@@ -91,23 +91,21 @@ 
	mb_intc: dw-apb-ictl@0xe0012000 {

		#interrupt-cells = <1>;

		compatible = "snps,dw-apb-ictl";

		reg = < 0xe0012000 0x200 >;

		reg = < 0x0 0xe0012000 0x0 0x200 >;

		interrupt-controller;

		interrupt-parent = <&core_intc>;

		interrupts = < 7 >;

	};



	memory {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x80000000 0x20000000>;

		device_type = "memory";

		reg = <0x80000000 0x1b000000>;	/* (512 - 32) MiB */

		/* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */

		reg = <0x0 0x80000000 0x0 0x1b000000>;	/* (512 - 32) MiB */

	};



	reserved-memory {

		#address-cells = <1>;

		#size-cells = <1>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		/*

		 * We just move frame buffer area to the very end of
@@ -118,7 +116,7 @@ 
		 */

		frame_buffer: frame_buffer@9e000000 {

			compatible = "shared-dma-pool";

			reg = <0x9e000000 0x2000000>;

			reg = <0x0 0x9e000000 0x0 0x2000000>;

			no-map;

		};

	};

arch/arc/boot/dts/axc003.dtsi

+10 −11
Original line number Diff line number Diff line
@@ -14,15 +14,15 @@ 


/ {

	compatible = "snps,arc";

	#address-cells = <1>;

	#size-cells = <1>;

	#address-cells = <2>;

	#size-cells = <2>;



	cpu_card {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;



		ranges = <0x00000000 0xf0000000 0x10000000>;

		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;



		core_clk: core_clk {

			#clock-cells = <0>;
@@ -94,30 +94,29 @@ 
	mb_intc: dw-apb-ictl@0xe0012000 {

		#interrupt-cells = <1>;

		compatible = "snps,dw-apb-ictl";

		reg = < 0xe0012000 0x200 >;

		reg = < 0x0 0xe0012000 0x0 0x200 >;

		interrupt-controller;

		interrupt-parent = <&core_intc>;

		interrupts = < 24 >;

	};



	memory {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x80000000 0x40000000>;

		device_type = "memory";

		reg = <0x80000000 0x20000000>;	/* 512MiB */

		/* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */

		reg = <0x0 0x80000000 0x0 0x20000000	/* 512 MiB low mem */

		       0x1 0xc0000000 0x0 0x40000000>;	/* 1 GiB highmem */

	};



	reserved-memory {

		#address-cells = <1>;

		#size-cells = <1>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		/*

		 * Move frame buffer out of IOC aperture (0x8z-0xAz).

		 */

		frame_buffer: frame_buffer@be000000 {

			compatible = "shared-dma-pool";

			reg = <0xbe000000 0x2000000>;

			reg = <0x0 0xbe000000 0x0 0x2000000>;

			no-map;

		};

	};

arch/arc/boot/dts/axc003_idu.dtsi

+10 −11
Original line number Diff line number Diff line
@@ -14,15 +14,15 @@ 


/ {

	compatible = "snps,arc";

	#address-cells = <1>;

	#size-cells = <1>;

	#address-cells = <2>;

	#size-cells = <2>;



	cpu_card {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;



		ranges = <0x00000000 0xf0000000 0x10000000>;

		ranges = <0x00000000 0x0 0xf0000000 0x10000000>;



		core_clk: core_clk {

			#clock-cells = <0>;
@@ -100,30 +100,29 @@ 
	mb_intc: dw-apb-ictl@0xe0012000 {

		#interrupt-cells = <1>;

		compatible = "snps,dw-apb-ictl";

		reg = < 0xe0012000 0x200 >;

		reg = < 0x0 0xe0012000 0x0 0x200 >;

		interrupt-controller;

		interrupt-parent = <&idu_intc>;

		interrupts = <0>;

	};



	memory {

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x80000000 0x40000000>;

		device_type = "memory";

		reg = <0x80000000 0x20000000>;	/* 512MiB */

		/* CONFIG_KERNEL_RAM_BASE_ADDRESS needs to match low mem start */

		reg = <0x0 0x80000000 0x0 0x20000000	/* 512 MiB low mem */

		       0x1 0xc0000000 0x0 0x40000000>;	/* 1 GiB highmem */

	};



	reserved-memory {

		#address-cells = <1>;

		#size-cells = <1>;

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		/*

		 * Move frame buffer out of IOC aperture (0x8z-0xAz).

		 */

		frame_buffer: frame_buffer@be000000 {

			compatible = "shared-dma-pool";

			reg = <0xbe000000 0x2000000>;

			reg = <0x0 0xbe000000 0x0 0x2000000>;

			no-map;

		};

	};

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