Commit 05a8256c authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile 

Pull arch/tile updates from Chris Metcalf:
 "These are a grab bag of changes to improve debugging and respond to a
  variety of issues raised on LKML over the last couple of months"

* git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile:
  tile: avoid a "label not used" warning in do_page_fault()
  tile: vdso: use raw_read_seqcount_begin() in vdso
  tile: force CONFIG_TILEGX if ARCH != tilepro
  tile: improve stack backtrace
  tile: fix "odd fault" warning for stack backtraces
  tile: set up initial stack top to honor STACK_TOP_DELTA
  tile: support delivering NMIs for multicore backtrace
  drivers/tty/hvc/hvc_tile.c: properly return -EAGAIN
  tile: add <asm/word-at-a-time.h> and enable support functions
  tile: use READ_ONCE() in arch_spin_is_locked()
  tile: modify arch_spin_unlock_wait() semantics
parents 0161b6e0 5316a64c

arch/tile/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -24,11 +24,14 @@ config TILE 
	select MODULES_USE_ELF_RELA

	select HAVE_ARCH_TRACEHOOK

	select HAVE_SYSCALL_TRACEPOINTS

	select USER_STACKTRACE_SUPPORT

	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE

	select HAVE_DEBUG_STACKOVERFLOW

	select ARCH_WANT_FRAME_POINTERS

	select HAVE_CONTEXT_TRACKING

	select EDAC_SUPPORT

	select GENERIC_STRNCPY_FROM_USER

	select GENERIC_STRNLEN_USER



# FIXME: investigate whether we need/want these options.

#	select HAVE_IOREMAP_PROT
@@ -125,8 +128,10 @@ config HVC_TILE 
	select HVC_IRQ if TILEGX

	def_bool y



# Building with ARCH=tilegx (or ARCH=tile) implies using the

# 64-bit TILE-Gx toolchain, so force CONFIG_TILEGX on.

config TILEGX

	bool "Building for TILE-Gx (64-bit) processor"

	def_bool ARCH != "tilepro"

	select SPARSE_IRQ

	select GENERIC_IRQ_LEGACY_ALLOC_HWIRQ

	select HAVE_FUNCTION_TRACER

arch/tile/include/asm/irq.h

+5 −0
Original line number Diff line number Diff line
@@ -78,4 +78,9 @@ void tile_irq_activate(unsigned int irq, int tile_irq_type); 


void setup_irq_regs(void);



#ifdef __tilegx__

void arch_trigger_all_cpu_backtrace(bool self);

#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace

#endif



#endif /* _ASM_TILE_IRQ_H */

arch/tile/include/asm/processor.h

+0 −2
Original line number Diff line number Diff line
@@ -111,8 +111,6 @@ struct thread_struct { 
	unsigned long long interrupt_mask;

	/* User interrupt-control 0 state */

	unsigned long intctrl_0;

	/* Is this task currently doing a backtrace? */

	bool in_backtrace;

	/* Any other miscellaneous processor state bits */

	unsigned long proc_status;

#if !CHIP_HAS_FIXED_INTVEC_BASE()

arch/tile/include/asm/spinlock_32.h

+5 −1
Original line number Diff line number Diff line
@@ -41,8 +41,12 @@ static inline int arch_spin_is_locked(arch_spinlock_t *lock) 
	 * to claim the lock is held, since it will be momentarily

	 * if not already.  There's no need to wait for a "valid"

	 * lock->next_ticket to become available.

	 * Use READ_ONCE() to ensure that calling this in a loop is OK.

	 */

	return lock->next_ticket != lock->current_ticket;

	int curr = READ_ONCE(lock->current_ticket);

	int next = READ_ONCE(lock->next_ticket);



	return next != curr;

}



void arch_spin_lock(arch_spinlock_t *lock);

arch/tile/include/asm/spinlock_64.h

+4 −1
Original line number Diff line number Diff line
@@ -18,6 +18,8 @@ 
#ifndef _ASM_TILE_SPINLOCK_64_H

#define _ASM_TILE_SPINLOCK_64_H



#include <linux/compiler.h>



/* Shifts and masks for the various fields in "lock". */

#define __ARCH_SPIN_CURRENT_SHIFT	17

#define __ARCH_SPIN_NEXT_MASK		0x7fff
@@ -44,7 +46,8 @@ static inline u32 arch_spin_next(u32 val) 
/* The lock is locked if a task would have to wait to get it. */

static inline int arch_spin_is_locked(arch_spinlock_t *lock)

{

	u32 val = lock->lock;

	/* Use READ_ONCE() to ensure that calling this in a loop is OK. */

	u32 val = READ_ONCE(lock->lock);

	return arch_spin_current(val) != arch_spin_next(val);

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE