drm/i915: Invariably invalidate before ctx switch (057f6a8a) · Commits · 戴 / test

We have been setting the bit which was originally BIOS dependent since: commit Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Sun Jan 20 16:33:32 2013 +0000 drm/i915: GFX_MODE Flush TLB Invalidate Mode must be '1' for scanline waits Therefore, we do not need to try to figure it out dynamically and we can just always invalidate the TLBs. It's a partial revert of: commit Author: Ben Widawsky <ben@bwidawsk.net> Date: Mon Jun 4 14:42:50 2012 -0700 drm/i915: possibly invalidate TLB before context switch The original commit attempted to only invalidate when necessary (very much a relic from the old days). Now, we can just always invalidate. I guess the old TODO still exists. Since we seem to have abandoned ILK contexts however, there isn't much point in even remembering. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:

Ben Widawsky <ben@bwidawsk.net> Reviewed-by:

Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:

Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/i915_gem_context.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -596,7 +596,7 @@ mi_set_context(struct intel_ring_buffer *ring,
		* explicitly, so we rely on the value at ring init, stored in
		* itlb_before_ctx_switch.
		*/
		if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
		if (IS_GEN6(ring->dev)) {
		ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
		if (ret)
		return ret;

drivers/gpu/drm/i915/intel_ringbuffer.c

+0 −7

Original line number	Diff line number	Diff line
		@@ -612,13 +612,6 @@ static int init_render_ring(struct intel_ring_buffer *ring)
		*/
		I915_WRITE(CACHE_MODE_0,
		_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));

		/* This is not explicitly set for GEN6, so read the register.
		* see intel_ring_mi_set_context() for why we care.
		* TODO: consider explicitly setting the bit for GEN5
		*/
		ring->itlb_before_ctx_switch =
		!!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_EXPLICIT);
		}

		if (INTEL_INFO(dev)->gen >= 6)

drivers/gpu/drm/i915/intel_ringbuffer.h

+0 −4

Original line number	Diff line number	Diff line
		@@ -152,10 +152,6 @@ struct intel_ring_buffer {

		wait_queue_head_t irq_queue;

		/**
		* Do an explicit TLB flush before MI_SET_CONTEXT
		*/
		bool itlb_before_ctx_switch;
		struct i915_hw_context *default_context;
		struct i915_hw_context *last_context;

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