Commit 057e6a8c authored May 23, 2011 by Andy Lutomirski Committed by Thomas Gleixner May 24, 2011

x86-64: Remove unnecessary barrier in vread_tsc

RDTSC is completely unordered on modern Intel and AMD CPUs.  The
Intel manual says that lfence;rdtsc causes all previous instructions
to complete before the tsc is read, and the AMD manual says to use
mfence;rdtsc to do the same thing.

From a decent amount of testing [1] this is enough to make rdtsc
be ordered with respect to subsequent loads across a wide variety
of CPUs.

On Sandy Bridge (i7-2600), this improves a loop of
clock_gettime(CLOCK_MONOTONIC) by more than 5 ns/iter.

[1] https://lkml.org/lkml/2011/4/18/350



Signed-off-by: Andy Lutomirski <luto@mit.edu>
Cc: Andi Kleen <andi@firstfloor.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Eric Dumazet <eric.dumazet@gmail.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Borislav Petkov <bp@amd64.org>
Link: http://lkml.kernel.org/r/%3C1c158b9d74338aa5361f96dd473d0e6a58235302.1306156808.git.luto%40mit.edu%3E


Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

parent 8c49d9a7

arch/x86/kernel/tsc.c

+5 −4

Original line number	Diff line number	Diff line
		@@ -769,13 +769,14 @@ static cycle_t __vsyscall_fn vread_tsc(void)
		cycle_t ret;

		/*
		* Surround the RDTSC by barriers, to make sure it's not
		* speculated to outside the seqlock critical section and
		* does not cause time warps:
		* Empirically, a fence (of type that depends on the CPU)
		* before rdtsc is enough to ensure that rdtsc is ordered
		* with respect to loads. The various CPU manuals are unclear
		* as to whether rdtsc can be reordered with later loads,
		* but no one has ever seen it happen.
		*/
		rdtsc_barrier();
		ret = (cycle_t)vget_cycles();
		rdtsc_barrier();

		return ret >= VVAR(vsyscall_gtod_data).clock.cycle_last ?
		ret : VVAR(vsyscall_gtod_data).clock.cycle_last;

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