firmware: xilinx: Add ZynqMP aes API for AES functionality (057a0fb6) · Commits · 戴 / test

drivers/firmware/xilinx/zynqmp.c

+25 −0

Original line number	Diff line number	Diff line
		@@ -707,6 +707,30 @@ static int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities,
		qos, ack, NULL);
		}

		/**
		* zynqmp_pm_aes - Access AES hardware to encrypt/decrypt the data using
		* AES-GCM core.
		* @address: Address of the AesParams structure.
		* @out: Returned output value
		*
		* Return: Returns status, either success or error code.
		*/
		static int zynqmp_pm_aes_engine(const u64 address, u32 *out)
		{
		u32 ret_payload[PAYLOAD_ARG_CNT];
		int ret;

		if (!out)
		return -EINVAL;

		ret = zynqmp_pm_invoke_fn(PM_SECURE_AES, upper_32_bits(address),
		lower_32_bits(address),
		0, 0, ret_payload);
		*out = ret_payload[1];

		return ret;
		}

		static const struct zynqmp_eemi_ops eemi_ops = {
		.get_api_version = zynqmp_pm_get_api_version,
		.get_chipid = zynqmp_pm_get_chipid,
		@@ -730,6 +754,7 @@ static const struct zynqmp_eemi_ops eemi_ops = {
		.set_requirement = zynqmp_pm_set_requirement,
		.fpga_load = zynqmp_pm_fpga_load,
		.fpga_get_status = zynqmp_pm_fpga_get_status,
		.aes = zynqmp_pm_aes_engine,
		};

		/**

+2 −0

Original line number	Diff line number	Diff line
		@@ -82,6 +82,7 @@ enum pm_api_id {
		PM_CLOCK_GETRATE,
		PM_CLOCK_SETPARENT,
		PM_CLOCK_GETPARENT,
		PM_SECURE_AES = 47,
		PM_FEATURE_CHECK = 63,
		PM_API_MAX,
		};
		@@ -315,6 +316,7 @@ struct zynqmp_eemi_ops {
		const u32 capabilities,
		const u32 qos,
		const enum zynqmp_pm_request_ack ack);
		int (aes)(const u64 address, u32 out);
		};

		int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1,