Unverified Commit 05635c14 authored by Jungseung Lee's avatar Jungseung Lee Committed by Tudor Ambarus
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mtd: spi-nor: Add SR 4bit block protection support 



Currently we are supporting block protection only for flash chips with
3 block protection bits (BP0-2) in the SR register.

Enable block protection support for flashes with 4 block protection bits
(BP0-3).

Add a flash_info flag for flashes that describe 4 block protection bits.
Add another flash_info flag for flashes in which BP3 bit is not adjacent
to the BP0-2 bits.

Tested with a n25q512ax3 (BP0-3) and w25q128 (BP0-2).

Signed-off-by: default avatarJungseung Lee <js07.lee@samsung.com>
Reviewed-by: default avatarMichael Walle <michael@walle.cc>
Tested-by: default avatarMichael Walle <michael@walle.cc>
Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
parent 2d284768

drivers/mtd/spi-nor/core.c

+48 −18
Original line number Diff line number Diff line
@@ -1536,13 +1536,34 @@ erase_err: 
	return ret;

}



static u8 spi_nor_get_sr_bp_mask(struct spi_nor *nor)

{

	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;



	if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6)

		return mask | SR_BP3_BIT6;



	if (nor->flags & SNOR_F_HAS_4BIT_BP)

		return mask | SR_BP3;



	return mask;

}



static u8 spi_nor_get_sr_tb_mask(struct spi_nor *nor)

{

	if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)

		return SR_TB_BIT6;

	else

		return SR_TB_BIT5;

}



static u64 spi_nor_get_min_prot_length_sr(struct spi_nor *nor)

{

	unsigned int bp_slots, bp_slots_needed;

	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;

	u8 mask = spi_nor_get_sr_bp_mask(nor);



	/* Reserved one for "protect none" and one for "protect all". */

	bp_slots = (mask >> SR_BP_SHIFT) + 1 - 2;

	bp_slots = (1 << hweight8(mask)) - 2;

	bp_slots_needed = ilog2(nor->info->n_sectors);



	if (bp_slots_needed > bp_slots)
@@ -1557,12 +1578,14 @@ static void spi_nor_get_locked_range_sr(struct spi_nor *nor, u8 sr, loff_t *ofs, 
{

	struct mtd_info *mtd = &nor->mtd;

	u64 min_prot_len;

	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;

	u8 tb_mask = SR_TB_BIT5;

	u8 bp = (sr & mask) >> SR_BP_SHIFT;

	u8 mask = spi_nor_get_sr_bp_mask(nor);

	u8 tb_mask = spi_nor_get_sr_tb_mask(nor);

	u8 bp, val = sr & mask;



	if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)

		tb_mask = SR_TB_BIT6;

	if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3_BIT6)

		val = (val & ~SR_BP3_BIT6) | SR_BP3;



	bp = val >> SR_BP_SHIFT;



	if (!bp) {

		/* No protection */
@@ -1620,7 +1643,8 @@ static int spi_nor_is_unlocked_sr(struct spi_nor *nor, loff_t ofs, uint64_t len, 


/*

 * Lock a region of the flash. Compatible with ST Micro and similar flash.

 * Supports the block protection bits BP{0,1,2} in the status register

 * Supports the block protection bits BP{0,1,2}/BP{0,1,2,3} in the status

 * register

 * (SR). Does not support these features found in newer SR bitfields:

 *   - SEC: sector/block protect - only handle SEC=0 (block protect)

 *   - CMP: complement protect - only support CMP=0 (range is not complemented)
@@ -1655,8 +1679,8 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 
	struct mtd_info *mtd = &nor->mtd;

	u64 min_prot_len;

	int ret, status_old, status_new;

	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;

	u8 tb_mask = SR_TB_BIT5;

	u8 mask = spi_nor_get_sr_bp_mask(nor);

	u8 tb_mask = spi_nor_get_sr_tb_mask(nor);

	u8 pow, val;

	loff_t lock_len;

	bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
@@ -1693,9 +1717,6 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 
	else

		lock_len = ofs + len;



	if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)

		tb_mask = SR_TB_BIT6;



	if (lock_len == mtd->size) {

		val = mask;

	} else {
@@ -1703,6 +1724,9 @@ static int spi_nor_sr_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) 
		pow = ilog2(lock_len) - ilog2(min_prot_len) + 1;

		val = pow << SR_BP_SHIFT;



		if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)

			val = (val & ~SR_BP3) | SR_BP3_BIT6;



		if (val & ~mask)

			return -EINVAL;
@@ -1740,8 +1764,8 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 
	struct mtd_info *mtd = &nor->mtd;

	u64 min_prot_len;

	int ret, status_old, status_new;

	u8 mask = SR_BP2 | SR_BP1 | SR_BP0;

	u8 tb_mask = SR_TB_BIT5;

	u8 mask = spi_nor_get_sr_bp_mask(nor);

	u8 tb_mask = spi_nor_get_sr_tb_mask(nor);

	u8 pow, val;

	loff_t lock_len;

	bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
@@ -1778,9 +1802,6 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 
	else

		lock_len = ofs;



	if (nor->flags & SNOR_F_HAS_SR_TB_BIT6)

		tb_mask = SR_TB_BIT6;



	if (lock_len == 0) {

		val = 0; /* fully unlocked */

	} else {
@@ -1788,6 +1809,9 @@ static int spi_nor_sr_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) 
		pow = ilog2(lock_len) - ilog2(min_prot_len) + 1;

		val = pow << SR_BP_SHIFT;



		if (nor->flags & SNOR_F_HAS_SR_BP3_BIT6 && val & SR_BP3)

			val = (val & ~SR_BP3) | SR_BP3_BIT6;



		/* Some power-of-two sizes are not supported */

		if (val & ~mask)

			return -EINVAL;
@@ -3147,6 +3171,12 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, 
	if (info->flags & USE_CLSR)

		nor->flags |= SNOR_F_USE_CLSR;



	if (info->flags & SPI_NOR_4BIT_BP) {

		nor->flags |= SNOR_F_HAS_4BIT_BP;

		if (info->flags & SPI_NOR_BP3_SR_BIT6)

			nor->flags |= SNOR_F_HAS_SR_BP3_BIT6;

	}



	if (info->flags & SPI_NOR_NO_ERASE)

		mtd->flags |= MTD_NO_ERASE;

drivers/mtd/spi-nor/core.h

+10 −0
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@ enum spi_nor_option_flags { 
	SNOR_F_HAS_16BIT_SR	= BIT(9),

	SNOR_F_NO_READ_CR	= BIT(10),

	SNOR_F_HAS_SR_TB_BIT6	= BIT(11),

	SNOR_F_HAS_4BIT_BP      = BIT(12),

	SNOR_F_HAS_SR_BP3_BIT6  = BIT(13),

};



struct spi_nor_read_command {
@@ -301,6 +303,14 @@ struct flash_info { 
					 * status register. Must be used with

					 * SPI_NOR_HAS_TB.

					 */

#define SPI_NOR_4BIT_BP		BIT(17) /*

					 * Flash SR has 4 bit fields (BP0-3)

					 * for block protection.

					 */

#define SPI_NOR_BP3_SR_BIT6	BIT(18) /*

					 * BP3 is bit 6 of status register.

					 * Must be used with SPI_NOR_4BIT_BP.

					 */



	/* Part specific fixup hooks. */

	const struct spi_nor_fixups *fixups;

include/linux/mtd/spi-nor.h

+2 −0
Original line number Diff line number Diff line
@@ -111,7 +111,9 @@ 
#define SR_BP0			BIT(2)	/* Block protect 0 */

#define SR_BP1			BIT(3)	/* Block protect 1 */

#define SR_BP2			BIT(4)	/* Block protect 2 */

#define SR_BP3			BIT(5)	/* Block protect 3 */

#define SR_TB_BIT5		BIT(5)	/* Top/Bottom protect */

#define SR_BP3_BIT6		BIT(6)	/* Block protect 3 */

#define SR_TB_BIT6		BIT(6)	/* Top/Bottom protect */

#define SR_SRWD			BIT(7)	/* SR write protect */

/* Spansion/Cypress specific status bits */

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