soc: mediatek: Refactor sram control (0545aa1b) · Commits · 戴 / test

drivers/soc/mediatek/mtk-scpsys.c

+53 −27

Original line number	Diff line number	Diff line
		@@ -230,12 +230,57 @@ static int scpsys_clk_enable(struct clk *clk[], int max_num)
		return ret;
		}

		static int scpsys_sram_enable(struct scp_domain scpd, void __iomem ctl_addr)
		{
		u32 val;
		u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
		int tmp;

		val = readl(ctl_addr);
		val &= ~scpd->data->sram_pdn_bits;
		writel(val, ctl_addr);

		/* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
		if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
		/*
		* Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
		* MT7622_POWER_DOMAIN_WB and thus just a trivial setup
		* is applied here.
		*/
		usleep_range(12000, 12100);
		} else {
		/* Either wait until SRAM_PDN_ACK all 1 or 0 */
		int ret = readl_poll_timeout(ctl_addr, tmp,
		(tmp & pdn_ack) == 0,
		MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
		if (ret < 0)
		return ret;
		}

		return 0;
		}

		static int scpsys_sram_disable(struct scp_domain scpd, void __iomem ctl_addr)
		{
		u32 val;
		u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
		int tmp;

		val = readl(ctl_addr);
		val \|= scpd->data->sram_pdn_bits;
		writel(val, ctl_addr);

		/* Either wait until SRAM_PDN_ACK all 1 or 0 */
		return readl_poll_timeout(ctl_addr, tmp,
		(tmp & pdn_ack) == pdn_ack,
		MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
		}

		static int scpsys_power_on(struct generic_pm_domain *genpd)
		{
		struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
		struct scp *scp = scpd->scp;
		void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
		u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
		u32 val;
		int ret, tmp;

		@@ -247,6 +292,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
		if (ret)
		goto err_clk;

		/* subsys power on */
		val = readl(ctl_addr);
		val \|= PWR_ON_BIT;
		writel(val, ctl_addr);
		@@ -268,24 +314,9 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
		val \|= PWR_RST_B_BIT;
		writel(val, ctl_addr);

		val &= ~scpd->data->sram_pdn_bits;
		writel(val, ctl_addr);

		/* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
		if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
		/*
		* Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
		* MT7622_POWER_DOMAIN_WB and thus just a trivial setup is
		* applied here.
		*/
		usleep_range(12000, 12100);

		} else {
		ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == 0,
		MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
		ret = scpsys_sram_enable(scpd, ctl_addr);
		if (ret < 0)
		goto err_pwr_ack;
		}

		if (scpd->data->bus_prot_mask) {
		ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
		@@ -312,7 +343,6 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
		struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
		struct scp *scp = scpd->scp;
		void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
		u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
		u32 val;
		int ret, tmp;

		@@ -324,16 +354,12 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
		goto out;
		}

		val = readl(ctl_addr);
		val \|= scpd->data->sram_pdn_bits;
		writel(val, ctl_addr);

		/* wait until SRAM_PDN_ACK all 1 */
		ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == pdn_ack,
		MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
		ret = scpsys_sram_disable(scpd, ctl_addr);
		if (ret < 0)
		goto out;

		/* subsys power off */
		val = readl(ctl_addr);
		val \|= PWR_ISO_BIT;
		writel(val, ctl_addr);

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