Commit 04df6ad9 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/misc' 

  - Fix Broadcom iProc quirk so it's applied regardless of whether the
    iproc driver is built-in or a module (Wei Liu)

  - Add extra delay when resuming AMD Ryzen5/7 XHCI controllers from D3hot
    so they work after resume from runtime suspend or suspend-to-idle
    (Daniel Drake)

  - Fix pci_alloc_irq_vectors() function name typo in docs (Zenghui Yu)

* pci/misc:
  Documentation: PCI: Fix pci_alloc_irq_vectors() function name typo
  PCI: Increase D3 delay for AMD Ryzen5/7 XHCI controllers
  PCI: Add generic quirk for increasing D3hot delay
  PCI: iproc: Apply quirk_paxc_bridge() for module as well as built-in
parents ba51b718 7730c3be

Documentation/PCI/msi-howto.rst

+1 −1
Original line number Diff line number Diff line
@@ -283,5 +283,5 @@ or disabled (0). If 0 is found in any of the msi_bus files belonging 
to bridges between the PCI root and the device, MSIs are disabled.



It is also worth checking the device driver to see whether it supports MSIs.

For example, it may contain calls to pci_irq_alloc_vectors() with the

For example, it may contain calls to pci_alloc_irq_vectors() with the

PCI_IRQ_MSI or PCI_IRQ_MSIX flags.

drivers/pci/controller/pcie-iproc.c

+24 −0
Original line number Diff line number Diff line
@@ -1588,6 +1588,30 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, 
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804,

			quirk_paxc_disable_msi_parsing);



static void quirk_paxc_bridge(struct pci_dev *pdev)

{

	/*

	 * The PCI config space is shared with the PAXC root port and the first

	 * Ethernet device.  So, we need to workaround this by telling the PCI

	 * code that the bridge is not an Ethernet device.

	 */

	if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)

		pdev->class = PCI_CLASS_BRIDGE_PCI << 8;



	/*

	 * MPSS is not being set properly (as it is currently 0).  This is

	 * because that area of the PCI config space is hard coded to zero, and

	 * is not modifiable by firmware.  Set this to 2 (e.g., 512 byte MPS)

	 * so that the MPS can be set to the real max value.

	 */

	pdev->pcie_mpss = 2;

}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);



MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");

MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");

MODULE_LICENSE("GPL v2");

drivers/pci/quirks.c

+28 −33
Original line number Diff line number Diff line
@@ -1871,19 +1871,40 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260a, quirk_intel_pcie_pm);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL,	0x260b, quirk_intel_pcie_pm);



static void quirk_radeon_pm(struct pci_dev *dev)

static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay)

{

	if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&

	    dev->subsystem_device == 0x00e2) {

		if (dev->d3_delay < 20) {

			dev->d3_delay = 20;

			pci_info(dev, "extending delay after power-on from D3 to %d msec\n",

	if (dev->d3_delay >= delay)

		return;



	dev->d3_delay = delay;

	pci_info(dev, "extending delay after power-on from D3hot to %d msec\n",

		 dev->d3_delay);

}

	}



static void quirk_radeon_pm(struct pci_dev *dev)

{

	if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&

	    dev->subsystem_device == 0x00e2)

		quirk_d3hot_delay(dev, 20);

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);



/*

 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle.

 * https://bugzilla.kernel.org/show_bug.cgi?id=205587

 *

 * The kernel attempts to transition these devices to D3cold, but that seems

 * to be ineffective on the platforms in question; the PCI device appears to

 * remain on in D3hot state. The D3hot-to-D0 transition then requires an

 * extended delay in order to succeed.

 */

static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev)

{

	quirk_d3hot_delay(dev, 20);

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot);

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot);



#ifdef CONFIG_X86_IO_APIC

static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)

{
@@ -2381,32 +2402,6 @@ DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 
			 PCI_DEVICE_ID_TIGON3_5719,

			 quirk_brcm_5719_limit_mrrs);



#ifdef CONFIG_PCIE_IPROC_PLATFORM

static void quirk_paxc_bridge(struct pci_dev *pdev)

{

	/*

	 * The PCI config space is shared with the PAXC root port and the first

	 * Ethernet device.  So, we need to workaround this by telling the PCI

	 * code that the bridge is not an Ethernet device.

	 */

	if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)

		pdev->class = PCI_CLASS_BRIDGE_PCI << 8;



	/*

	 * MPSS is not being set properly (as it is currently 0).  This is

	 * because that area of the PCI config space is hard coded to zero, and

	 * is not modifiable by firmware.  Set this to 2 (e.g., 512 byte MPS)

	 * so that the MPS can be set to the real max value.

	 */

	pdev->pcie_mpss = 2;

}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd750, quirk_paxc_bridge);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd802, quirk_paxc_bridge);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0xd804, quirk_paxc_bridge);

#endif



/*

 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to

 * hide device 6 which configures the overflow device access containing the

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