Commit 04d80dbe authored Feb 25, 2020 by Heyi Guo Committed by Marc Zyngier Mar 08, 2020

irqchip/gic-v3-its: Fix access width for gicr_syncr



GICR_SYNCR is a 32bit register, so it is better to access it with
32bit access width, though we have not seen any real problem.

Signed-off-by: Heyi Guo <guoheyi@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20200225090023.28020-1-guoheyi@huawei.com

parent 47beed51

drivers/irqchip/irq-gic-v3-its.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1321,7 +1321,7 @@ static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)

		static void wait_for_syncr(void __iomem *rdbase)
		{
		while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
		while (readl_relaxed(rdbase + GICR_SYNCR) & 1)
		cpu_relax();
		}

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