Commit 04ad3011 authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab
Browse files

media: rc: fix several typos



Use codespell to fix lots of typos over frontends.

Manually verified to avoid false-positives.

Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
Acked-by: default avatarSean Young <sean@mess.org>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 8b72c18d
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+2 −2
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@@ -253,7 +253,7 @@ config IR_FINTEK
	depends on RC_CORE
	---help---
	   Say Y here to enable support for integrated infrared receiver
	   /transciever made by Fintek. This chip is found on assorted
	   /transceiver made by Fintek. This chip is found on assorted
	   Jetway motherboards (and of course, possibly others).

	   To compile this driver as a module, choose M here: the
@@ -287,7 +287,7 @@ config IR_NUVOTON
	depends on RC_CORE
	---help---
	   Say Y here to enable support for integrated infrared receiver
	   /transciever made by Nuvoton (formerly Winbond). This chip is
	   /transceiver made by Nuvoton (formerly Winbond). This chip is
	   found in the ASRock ION 330HT, as well as assorted Intel
	   DP55-series motherboards (and of course, possibly others).

+1 −1
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@@ -304,7 +304,7 @@ static const struct {
	{KIND_LITERAL,  0x7c, BTN_RIGHT},/* right btn down */
	{KIND_LITERAL,  0x7d, BTN_RIGHT},/* right btn up */

	/* Artificial "doubleclick" events are generated by the hardware.
	/* Artificial "double-click" events are generated by the hardware.
	 * They are mapped to the "side" and "extra" mouse buttons here. */
	{KIND_FILTERED, 0x7a, BTN_SIDE}, /* left dblclick */
	{KIND_FILTERED, 0x7e, BTN_EXTRA},/* right dblclick */
+1 −1
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@@ -184,7 +184,7 @@ static int ene_hw_detect(struct ene_device *dev)
	return 0;
}

/* Read properities of hw sample buffer */
/* Read properties of hw sample buffer */
static void ene_rx_setup_hw_buffer(struct ene_device *dev)
{
	u16 tmp;
+1 −1
Original line number Diff line number Diff line
@@ -118,7 +118,7 @@
#define ENE_CIRDAT_IN		0xFEC7


/* RLC configuration - sample period (1us resulution) + idle mode */
/* RLC configuration - sample period (1us resolution) + idle mode */
#define ENE_CIRRLC_CFG		0xFEC8
#define ENE_CIRRLC_CFG_OVERFLOW	0x80	/* interrupt on overflows if set */
#define ENE_DEFAULT_SAMPLE_PERIOD 50
+1 −1
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@@ -176,7 +176,7 @@ struct fintek_dev {
#define CIR_CR_IRCS		0x05 /* Before host writes command to IR, host
					must set to 1. When host finshes write
					command to IR, host must clear to 0. */
#define CIR_CR_COMMAND_DATA	0x06 /* Host read or write comand data */
#define CIR_CR_COMMAND_DATA	0x06 /* Host read or write command data */
#define CIR_CR_CLASS		0x07 /* 0xff = rx-only, 0x66 = rx + 2 tx,
					0x33 = rx + 1 tx */
#define CIR_CR_DEV_EN		0x30 /* bit0 = 1 enables CIR */
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