Commit 04816e67 authored by Sarthak Garg's avatar Sarthak Garg Committed by Ulf Hansson
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mmc: sdhci-msm: Update dll_config_3 as per HSR 



Update dll_config_3 as per the host clock frequency as specified in the
DLL Hardware Reference Guide.

Signed-off-by: default avatarSarthak Garg <sartgarg@codeaurora.org>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/1590139950-7288-5-git-send-email-sartgarg@codeaurora.org


Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 5c30f340

drivers/mmc/host/sdhci-msm.c

+13 −0
Original line number Diff line number Diff line
@@ -62,6 +62,9 @@ 
#define FINE_TUNE_MODE_EN	BIT(27)

#define BIAS_OK_SIGNAL		BIT(29)



#define DLL_CONFIG_3_LOW_FREQ_VAL	0x08

#define DLL_CONFIG_3_HIGH_FREQ_VAL	0x10



#define CORE_VENDOR_SPEC_POR_VAL 0xa9c

#define CORE_CLK_PWRSAVE	BIT(1)

#define CORE_HC_MCLK_SEL_DFLT	(2 << 8)
@@ -695,6 +698,16 @@ static int msm_init_cm_dll(struct sdhci_host *host) 
			ENABLE_DLL_LOCK_STATUS | BIAS_OK_SIGNAL;

		writel_relaxed(config, host->ioaddr +

				msm_offset->core_dll_usr_ctl);



		config = readl_relaxed(host->ioaddr +

				msm_offset->core_dll_config_3);

		config &= ~0xFF;

		if (msm_host->clk_rate < 150000000)

			config |= DLL_CONFIG_3_LOW_FREQ_VAL;

		else

			config |= DLL_CONFIG_3_HIGH_FREQ_VAL;

		writel_relaxed(config, host->ioaddr +

			msm_offset->core_dll_config_3);

	}



	config = readl_relaxed(host->ioaddr +

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