mmc: sdhci-of-esdhc: set the sd clock divisor value above 3 (04509d77) · Commits · 戴 / test

This patch is to set the sd clock divisor value above 3 in tuning mode Signed-off-by:

drivers/mmc/host/sdhci-of-esdhc.c

+8 −0

Original line number	Diff line number	Diff line
		@@ -830,9 +830,17 @@ static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode)
		struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
		struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
		bool hs400_tuning;
		unsigned int clk;
		u32 val;
		int ret;

		/* For tuning mode, the sd clock divisor value
		* must be larger than 3 according to reference manual.
		*/
		clk = esdhc->peripheral_clock / 3;
		if (host->clock > clk)
		esdhc_of_set_clock(host, clk);

		if (esdhc->quirk_limited_clk_division &&
		host->flags & SDHCI_HS400_TUNING)
		esdhc_of_set_clock(host, host->clock);