Commit 04474d3a authored by Bart Van Assche's avatar Bart Van Assche Committed by Martin K. Petersen
Browse files

scsi: qla2xxx: Change {RD,WRT}_REG_*() function names from upper case into lower case 

This was suggested by Daniel Wagner.

Link: https://lore.kernel.org/r/20200518211712.11395-12-bvanassche@acm.org


Cc: Nilesh Javali <njavali@marvell.com>
Cc: Quinn Tran <qutran@marvell.com>
Cc: Martin Wilck <mwilck@suse.com>
Cc: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: default avatarDaniel Wagner <dwagner@suse.de>
Reviewed-by: default avatarHimanshu Madhani <himanshu.madhani@oracle.com>
Reviewed-by: default avatarArun Easi <aeasi@marvell.com>
Signed-off-by: default avatarBart Van Assche <bvanassche@acm.org>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 37139da1

drivers/scsi/qla2xxx/qla_dbg.c

+291 −291

File changed.

Preview size limit exceeded, changes collapsed.

drivers/scsi/qla2xxx/qla_def.h

+13 −13
Original line number Diff line number Diff line
@@ -128,47 +128,47 @@ static inline uint32_t make_handle(uint16_t x, uint16_t y) 
 * I/O register

*/



static inline u8 RD_REG_BYTE(const volatile u8 __iomem *addr)

static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)

{

	return readb(addr);

}



static inline u16 RD_REG_WORD(const volatile __le16 __iomem *addr)

static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)

{

	return readw(addr);

}



static inline u32 RD_REG_DWORD(const volatile __le32 __iomem *addr)

static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)

{

	return readl(addr);

}



static inline u8 RD_REG_BYTE_RELAXED(const volatile u8 __iomem *addr)

static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)

{

	return readb_relaxed(addr);

}



static inline u16 RD_REG_WORD_RELAXED(const volatile __le16 __iomem *addr)

static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)

{

	return readw_relaxed(addr);

}



static inline u32 RD_REG_DWORD_RELAXED(const volatile __le32 __iomem *addr)

static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)

{

	return readl_relaxed(addr);

}



static inline void WRT_REG_BYTE(volatile u8 __iomem *addr, u8 data)

static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)

{

	return writeb(data, addr);

}



static inline void WRT_REG_WORD(volatile __le16 __iomem *addr, u16 data)

static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)

{

	return writew(data, addr);

}



static inline void WRT_REG_DWORD(volatile __le32 __iomem *addr, u32 data)

static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)

{

	return writel(data, addr);

}
@@ -956,18 +956,18 @@ typedef union { 
	  &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \

	 &(reg)->u.isp2300.mailbox0 + (num))

#define RD_MAILBOX_REG(ha, reg, num) \

	RD_REG_WORD(MAILBOX_REG(ha, reg, num))

	rd_reg_word(MAILBOX_REG(ha, reg, num))

#define WRT_MAILBOX_REG(ha, reg, num, data) \

	WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)

	wrt_reg_word(MAILBOX_REG(ha, reg, num), data)



#define FB_CMD_REG(ha, reg) \

	(IS_QLA2100(ha) || IS_QLA2200(ha) ? \

	 &(reg)->fb_cmd_2100 : \

	 &(reg)->u.isp2300.fb_cmd)

#define RD_FB_CMD_REG(ha, reg) \

	RD_REG_WORD(FB_CMD_REG(ha, reg))

	rd_reg_word(FB_CMD_REG(ha, reg))

#define WRT_FB_CMD_REG(ha, reg, data) \

	WRT_REG_WORD(FB_CMD_REG(ha, reg), data)

	wrt_reg_word(FB_CMD_REG(ha, reg), data)



typedef struct {

	uint32_t	out_mb;		/* outbound from driver */

drivers/scsi/qla2xxx/qla_init.c

+102 −103
Original line number Diff line number Diff line
@@ -2219,7 +2219,7 @@ qla2x00_initialize_adapter(scsi_qla_host_t *vha) 


	/* Check for secure flash support */

	if (IS_QLA28XX(ha)) {

		if (RD_REG_WORD(&reg->mailbox12) & BIT_0)

		if (rd_reg_word(&reg->mailbox12) & BIT_0)

			ha->flags.secure_adapter = 1;

		ql_log(ql_log_info, vha, 0xffff, "Secure Adapter: %s\n",

		    (ha->flags.secure_adapter) ? "Yes" : "No");
@@ -2357,7 +2357,7 @@ qla2100_pci_config(scsi_qla_host_t *vha) 


	/* Get PCI bus information. */

	spin_lock_irqsave(&ha->hardware_lock, flags);

	ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);

	ha->pci_attr = rd_reg_word(&reg->ctrl_status);

	spin_unlock_irqrestore(&ha->hardware_lock, flags);



	return QLA_SUCCESS;
@@ -2399,17 +2399,17 @@ qla2300_pci_config(scsi_qla_host_t *vha) 
		spin_lock_irqsave(&ha->hardware_lock, flags);



		/* Pause RISC. */

		WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);

		wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);

		for (cnt = 0; cnt < 30000; cnt++) {

			if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)

			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) != 0)

				break;



			udelay(10);

		}



		/* Select FPM registers. */

		WRT_REG_WORD(&reg->ctrl_status, 0x20);

		RD_REG_WORD(&reg->ctrl_status);

		wrt_reg_word(&reg->ctrl_status, 0x20);

		rd_reg_word(&reg->ctrl_status);



		/* Get the fb rev level */

		ha->fb_rev = RD_FB_CMD_REG(ha, reg);
@@ -2418,13 +2418,13 @@ qla2300_pci_config(scsi_qla_host_t *vha) 
			pci_clear_mwi(ha->pdev);



		/* Deselect FPM registers. */

		WRT_REG_WORD(&reg->ctrl_status, 0x0);

		RD_REG_WORD(&reg->ctrl_status);

		wrt_reg_word(&reg->ctrl_status, 0x0);

		rd_reg_word(&reg->ctrl_status);



		/* Release RISC module. */

		WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);

		wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);

		for (cnt = 0; cnt < 30000; cnt++) {

			if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)

			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0)

				break;



			udelay(10);
@@ -2439,7 +2439,7 @@ qla2300_pci_config(scsi_qla_host_t *vha) 


	/* Get PCI bus information. */

	spin_lock_irqsave(&ha->hardware_lock, flags);

	ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);

	ha->pci_attr = rd_reg_word(&reg->ctrl_status);

	spin_unlock_irqrestore(&ha->hardware_lock, flags);



	return QLA_SUCCESS;
@@ -2483,7 +2483,7 @@ qla24xx_pci_config(scsi_qla_host_t *vha) 


	/* Get PCI bus information. */

	spin_lock_irqsave(&ha->hardware_lock, flags);

	ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);

	ha->pci_attr = rd_reg_dword(&reg->ctrl_status);

	spin_unlock_irqrestore(&ha->hardware_lock, flags);



	return QLA_SUCCESS;
@@ -2587,36 +2587,36 @@ qla2x00_reset_chip(scsi_qla_host_t *vha) 


	if (!IS_QLA2100(ha)) {

		/* Pause RISC. */

		WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);

		wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);

		if (IS_QLA2200(ha) || IS_QLA2300(ha)) {

			for (cnt = 0; cnt < 30000; cnt++) {

				if ((RD_REG_WORD(&reg->hccr) &

				if ((rd_reg_word(&reg->hccr) &

				    HCCR_RISC_PAUSE) != 0)

					break;

				udelay(100);

			}

		} else {

			RD_REG_WORD(&reg->hccr);	/* PCI Posting. */

			rd_reg_word(&reg->hccr);	/* PCI Posting. */

			udelay(10);

		}



		/* Select FPM registers. */

		WRT_REG_WORD(&reg->ctrl_status, 0x20);

		RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */

		wrt_reg_word(&reg->ctrl_status, 0x20);

		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */



		/* FPM Soft Reset. */

		WRT_REG_WORD(&reg->fpm_diag_config, 0x100);

		RD_REG_WORD(&reg->fpm_diag_config);	/* PCI Posting. */

		wrt_reg_word(&reg->fpm_diag_config, 0x100);

		rd_reg_word(&reg->fpm_diag_config);	/* PCI Posting. */



		/* Toggle Fpm Reset. */

		if (!IS_QLA2200(ha)) {

			WRT_REG_WORD(&reg->fpm_diag_config, 0x0);

			RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */

			wrt_reg_word(&reg->fpm_diag_config, 0x0);

			rd_reg_word(&reg->fpm_diag_config); /* PCI Posting. */

		}



		/* Select frame buffer registers. */

		WRT_REG_WORD(&reg->ctrl_status, 0x10);

		RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */

		wrt_reg_word(&reg->ctrl_status, 0x10);

		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */



		/* Reset frame buffer FIFOs. */

		if (IS_QLA2200(ha)) {
@@ -2634,23 +2634,23 @@ qla2x00_reset_chip(scsi_qla_host_t *vha) 
		}



		/* Select RISC module registers. */

		WRT_REG_WORD(&reg->ctrl_status, 0);

		RD_REG_WORD(&reg->ctrl_status);		/* PCI Posting. */

		wrt_reg_word(&reg->ctrl_status, 0);

		rd_reg_word(&reg->ctrl_status);		/* PCI Posting. */



		/* Reset RISC processor. */

		WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);

		RD_REG_WORD(&reg->hccr);		/* PCI Posting. */

		wrt_reg_word(&reg->hccr, HCCR_RESET_RISC);

		rd_reg_word(&reg->hccr);		/* PCI Posting. */



		/* Release RISC processor. */

		WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);

		RD_REG_WORD(&reg->hccr);		/* PCI Posting. */

		wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);

		rd_reg_word(&reg->hccr);		/* PCI Posting. */

	}



	WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);

	WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);

	wrt_reg_word(&reg->hccr, HCCR_CLR_RISC_INT);

	wrt_reg_word(&reg->hccr, HCCR_CLR_HOST_INT);



	/* Reset ISP chip. */

	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);

	wrt_reg_word(&reg->ctrl_status, CSR_ISP_SOFT_RESET);



	/* Wait for RISC to recover from reset. */

	if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
@@ -2661,7 +2661,7 @@ qla2x00_reset_chip(scsi_qla_host_t *vha) 
		 */

		udelay(20);

		for (cnt = 30000; cnt; cnt--) {

			if ((RD_REG_WORD(&reg->ctrl_status) &

			if ((rd_reg_word(&reg->ctrl_status) &

			    CSR_ISP_SOFT_RESET) == 0)

				break;

			udelay(100);
@@ -2670,13 +2670,13 @@ qla2x00_reset_chip(scsi_qla_host_t *vha) 
		udelay(10);



	/* Reset RISC processor. */

	WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);

	wrt_reg_word(&reg->hccr, HCCR_RESET_RISC);



	WRT_REG_WORD(&reg->semaphore, 0);

	wrt_reg_word(&reg->semaphore, 0);



	/* Release RISC processor. */

	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);

	RD_REG_WORD(&reg->hccr);			/* PCI Posting. */

	wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);

	rd_reg_word(&reg->hccr);			/* PCI Posting. */



	if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {

		for (cnt = 0; cnt < 30000; cnt++) {
@@ -2694,8 +2694,8 @@ qla2x00_reset_chip(scsi_qla_host_t *vha) 


	/* Disable RISC pause on FPM parity error. */

	if (!IS_QLA2100(ha)) {

		WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);

		RD_REG_WORD(&reg->hccr);		/* PCI Posting. */

		wrt_reg_word(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);

		rd_reg_word(&reg->hccr);		/* PCI Posting. */

	}



	spin_unlock_irqrestore(&ha->hardware_lock, flags);
@@ -2740,32 +2740,32 @@ qla24xx_reset_risc(scsi_qla_host_t *vha) 
	spin_lock_irqsave(&ha->hardware_lock, flags);



	/* Reset RISC. */

	WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);

	wrt_reg_dword(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);

	for (cnt = 0; cnt < 30000; cnt++) {

		if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)

		if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)

			break;



		udelay(10);

	}



	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))

	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE))

		set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);



	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,

	    "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",

	    RD_REG_DWORD(&reg->hccr),

	    RD_REG_DWORD(&reg->ctrl_status),

	    (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));

	    rd_reg_dword(&reg->hccr),

	    rd_reg_dword(&reg->ctrl_status),

	    (rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE));



	WRT_REG_DWORD(&reg->ctrl_status,

	wrt_reg_dword(&reg->ctrl_status,

	    CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);

	pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);



	udelay(100);



	/* Wait for firmware to complete NVRAM accesses. */

	RD_REG_WORD(&reg->mailbox0);

	for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&

	rd_reg_word(&reg->mailbox0);

	for (cnt = 10000; rd_reg_word(&reg->mailbox0) != 0 &&

	    rval == QLA_SUCCESS; cnt--) {

		barrier();

		if (cnt)
@@ -2779,26 +2779,26 @@ qla24xx_reset_risc(scsi_qla_host_t *vha) 


	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,

	    "HCCR: 0x%x, MailBox0 Status 0x%x\n",

	    RD_REG_DWORD(&reg->hccr),

	    RD_REG_WORD(&reg->mailbox0));

	    rd_reg_dword(&reg->hccr),

	    rd_reg_word(&reg->mailbox0));



	/* Wait for soft-reset to complete. */

	RD_REG_DWORD(&reg->ctrl_status);

	rd_reg_dword(&reg->ctrl_status);

	for (cnt = 0; cnt < 60; cnt++) {

		barrier();

		if ((RD_REG_DWORD(&reg->ctrl_status) &

		if ((rd_reg_dword(&reg->ctrl_status) &

		    CSRX_ISP_SOFT_RESET) == 0)

			break;



		udelay(5);

	}

	if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))

	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))

		set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);



	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,

	    "HCCR: 0x%x, Soft Reset status: 0x%x\n",

	    RD_REG_DWORD(&reg->hccr),

	    RD_REG_DWORD(&reg->ctrl_status));

	    rd_reg_dword(&reg->hccr),

	    rd_reg_dword(&reg->ctrl_status));



	/* If required, do an MPI FW reset now */

	if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
@@ -2817,17 +2817,17 @@ qla24xx_reset_risc(scsi_qla_host_t *vha) 
		}

	}



	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);

	RD_REG_DWORD(&reg->hccr);

	wrt_reg_dword(&reg->hccr, HCCRX_SET_RISC_RESET);

	rd_reg_dword(&reg->hccr);



	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);

	RD_REG_DWORD(&reg->hccr);

	wrt_reg_dword(&reg->hccr, HCCRX_REL_RISC_PAUSE);

	rd_reg_dword(&reg->hccr);



	WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);

	RD_REG_DWORD(&reg->hccr);

	wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_RESET);

	rd_reg_dword(&reg->hccr);



	RD_REG_WORD(&reg->mailbox0);

	for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&

	rd_reg_word(&reg->mailbox0);

	for (cnt = 60; rd_reg_word(&reg->mailbox0) != 0 &&

	    rval == QLA_SUCCESS; cnt--) {

		barrier();

		if (cnt)
@@ -2840,8 +2840,8 @@ qla24xx_reset_risc(scsi_qla_host_t *vha) 


	ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,

	    "Host Risc 0x%x, mailbox0 0x%x\n",

	    RD_REG_DWORD(&reg->hccr),

	     RD_REG_WORD(&reg->mailbox0));

	    rd_reg_dword(&reg->hccr),

	     rd_reg_word(&reg->mailbox0));



	spin_unlock_irqrestore(&ha->hardware_lock, flags);
@@ -2860,9 +2860,8 @@ qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) 
{

	struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;



	WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);

	*data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFSET);



	wrt_reg_dword(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);

	*data = rd_reg_dword(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFSET);

}



static void
@@ -2870,8 +2869,8 @@ qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) 
{

	struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;



	WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);

	WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFSET, data);

	wrt_reg_dword(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);

	wrt_reg_dword(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFSET, data);

}



static void
@@ -2887,7 +2886,7 @@ qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) 
	    vha->hw->pdev->subsystem_device != 0x0240)

		return;



	WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);

	wrt_reg_dword(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);

	udelay(100);



attempt:
@@ -2989,7 +2988,7 @@ qla2x00_chip_diag(scsi_qla_host_t *vha) 
	spin_lock_irqsave(&ha->hardware_lock, flags);



	/* Reset ISP chip. */

	WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);

	wrt_reg_word(&reg->ctrl_status, CSR_ISP_SOFT_RESET);



	/*

	 * We need to have a delay here since the card will not respond while
@@ -2999,7 +2998,7 @@ qla2x00_chip_diag(scsi_qla_host_t *vha) 
	data = qla2x00_debounce_register(&reg->ctrl_status);

	for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {

		udelay(5);

		data = RD_REG_WORD(&reg->ctrl_status);

		data = rd_reg_word(&reg->ctrl_status);

		barrier();

	}
@@ -3010,8 +3009,8 @@ qla2x00_chip_diag(scsi_qla_host_t *vha) 
	    "Reset register cleared by chip reset.\n");



	/* Reset RISC processor. */

	WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);

	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);

	wrt_reg_word(&reg->hccr, HCCR_RESET_RISC);

	wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);



	/* Workaround for QLA2312 PCI parity error */

	if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
@@ -3654,8 +3653,8 @@ qla2x00_setup_chip(scsi_qla_host_t *vha) 
	if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {

		/* Disable SRAM, Instruction RAM and GP RAM parity.  */

		spin_lock_irqsave(&ha->hardware_lock, flags);

		WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));

		RD_REG_WORD(&reg->hccr);

		wrt_reg_word(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));

		rd_reg_word(&reg->hccr);

		spin_unlock_irqrestore(&ha->hardware_lock, flags);

	}
@@ -3762,11 +3761,11 @@ enable_82xx_npiv: 
		spin_lock_irqsave(&ha->hardware_lock, flags);

		if (IS_QLA2300(ha))

			/* SRAM parity */

			WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);

			wrt_reg_word(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);

		else

			/* SRAM, Instruction RAM and GP RAM parity */

			WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);

		RD_REG_WORD(&reg->hccr);

			wrt_reg_word(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);

		rd_reg_word(&reg->hccr);

		spin_unlock_irqrestore(&ha->hardware_lock, flags);

	}
@@ -4010,11 +4009,11 @@ qla2x00_config_rings(struct scsi_qla_host *vha) 
	put_unaligned_le64(req->dma, &ha->init_cb->request_q_address);

	put_unaligned_le64(rsp->dma, &ha->init_cb->response_q_address);



	WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);

	WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);

	WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);

	WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);

	RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg));		/* PCI Posting. */

	wrt_reg_word(ISP_REQ_Q_IN(ha, reg), 0);

	wrt_reg_word(ISP_REQ_Q_OUT(ha, reg), 0);

	wrt_reg_word(ISP_RSP_Q_IN(ha, reg), 0);

	wrt_reg_word(ISP_RSP_Q_OUT(ha, reg), 0);

	rd_reg_word(ISP_RSP_Q_OUT(ha, reg));		/* PCI Posting. */

}



void
@@ -4076,15 +4075,15 @@ qla24xx_config_rings(struct scsi_qla_host *vha) 
		}

		icb->firmware_options_2 |= cpu_to_le32(BIT_23);



		WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);

		WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);

		WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);

		WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);

		wrt_reg_dword(&reg->isp25mq.req_q_in, 0);

		wrt_reg_dword(&reg->isp25mq.req_q_out, 0);

		wrt_reg_dword(&reg->isp25mq.rsp_q_in, 0);

		wrt_reg_dword(&reg->isp25mq.rsp_q_out, 0);

	} else {

		WRT_REG_DWORD(&reg->isp24.req_q_in, 0);

		WRT_REG_DWORD(&reg->isp24.req_q_out, 0);

		WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);

		WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);

		wrt_reg_dword(&reg->isp24.req_q_in, 0);

		wrt_reg_dword(&reg->isp24.req_q_out, 0);

		wrt_reg_dword(&reg->isp24.rsp_q_in, 0);

		wrt_reg_dword(&reg->isp24.rsp_q_out, 0);

	}



	qlt_24xx_config_rings(vha);
@@ -4098,7 +4097,7 @@ qla24xx_config_rings(struct scsi_qla_host *vha) 
	}



	/* PCI posting */

	RD_REG_WORD(&ioreg->hccr);

	rd_reg_word(&ioreg->hccr);

}



/**
@@ -4569,7 +4568,7 @@ qla2x00_nvram_config(scsi_qla_host_t *vha) 
	ha->nvram_size = sizeof(*nv);

	ha->nvram_base = 0;

	if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))

		if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)

		if ((rd_reg_word(&reg->ctrl_status) >> 14) == 1)

			ha->nvram_base = 0x80;



	/* Get NVRAM data and calculate checksum. */
@@ -7090,10 +7089,10 @@ qla2x00_reset_adapter(scsi_qla_host_t *vha) 
	ha->isp_ops->disable_intrs(ha);



	spin_lock_irqsave(&ha->hardware_lock, flags);

	WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);

	RD_REG_WORD(&reg->hccr);			/* PCI Posting. */

	WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);

	RD_REG_WORD(&reg->hccr);			/* PCI Posting. */

	wrt_reg_word(&reg->hccr, HCCR_RESET_RISC);

	rd_reg_word(&reg->hccr);			/* PCI Posting. */

	wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);

	rd_reg_word(&reg->hccr);			/* PCI Posting. */

	spin_unlock_irqrestore(&ha->hardware_lock, flags);



	return QLA_SUCCESS;
@@ -7114,10 +7113,10 @@ qla24xx_reset_adapter(scsi_qla_host_t *vha) 
	ha->isp_ops->disable_intrs(ha);



	spin_lock_irqsave(&ha->hardware_lock, flags);

	WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);

	RD_REG_DWORD(&reg->hccr);

	WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);

	RD_REG_DWORD(&reg->hccr);

	wrt_reg_dword(&reg->hccr, HCCRX_SET_RISC_RESET);

	rd_reg_dword(&reg->hccr);

	wrt_reg_dword(&reg->hccr, HCCRX_REL_RISC_PAUSE);

	rd_reg_dword(&reg->hccr);

	spin_unlock_irqrestore(&ha->hardware_lock, flags);



	if (IS_NOPOLLING_TYPE(ha))

drivers/scsi/qla2xxx/qla_inline.h

+3 −3
Original line number Diff line number Diff line
@@ -46,10 +46,10 @@ qla2x00_debounce_register(volatile uint16_t __iomem *addr) 
	volatile uint16_t second;



	do {

		first = RD_REG_WORD(addr);

		first = rd_reg_word(addr);

		barrier();

		cpu_relax();

		second = RD_REG_WORD(addr);

		second = rd_reg_word(addr);

	} while (first != second);



	return (first);
@@ -329,7 +329,7 @@ qla_83xx_start_iocbs(struct qla_qpair *qpair) 
	} else

		req->ring_ptr++;



	WRT_REG_DWORD(req->req_q_in, req->ring_index);

	wrt_reg_dword(req->req_q_in, req->ring_index);

}



static inline int

drivers/scsi/qla2xxx/qla_iocb.c

+32 −32
Original line number Diff line number Diff line
@@ -376,7 +376,7 @@ qla2x00_start_scsi(srb_t *sp) 
	/* Calculate the number of request entries needed. */

	req_cnt = ha->isp_ops->calc_req_entries(tot_dsds);

	if (req->cnt < (req_cnt + 2)) {

		cnt = RD_REG_WORD_RELAXED(ISP_REQ_Q_OUT(ha, reg));

		cnt = rd_reg_word_relaxed(ISP_REQ_Q_OUT(ha, reg));

		if (req->ring_index < cnt)

			req->cnt = cnt - req->ring_index;

		else
@@ -428,8 +428,8 @@ qla2x00_start_scsi(srb_t *sp) 
	sp->flags |= SRB_DMA_VALID;



	/* Set chip new ring index. */

	WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), req->ring_index);

	RD_REG_WORD_RELAXED(ISP_REQ_Q_IN(ha, reg));	/* PCI Posting. */

	wrt_reg_word(ISP_REQ_Q_IN(ha, reg), req->ring_index);

	rd_reg_word_relaxed(ISP_REQ_Q_IN(ha, reg));	/* PCI Posting. */



	/* Manage unprocessed RIO/ZIO commands in response queue. */

	if (vha->flags.process_response_queue &&
@@ -472,21 +472,21 @@ qla2x00_start_iocbs(struct scsi_qla_host *vha, struct req_que *req) 


		/* Set chip new ring index. */

		if (ha->mqenable || IS_QLA27XX(ha) || IS_QLA28XX(ha)) {

			WRT_REG_DWORD(req->req_q_in, req->ring_index);

			wrt_reg_dword(req->req_q_in, req->ring_index);

		} else if (IS_QLA83XX(ha)) {

			WRT_REG_DWORD(req->req_q_in, req->ring_index);

			RD_REG_DWORD_RELAXED(&ha->iobase->isp24.hccr);

			wrt_reg_dword(req->req_q_in, req->ring_index);

			rd_reg_dword_relaxed(&ha->iobase->isp24.hccr);

		} else if (IS_QLAFX00(ha)) {

			WRT_REG_DWORD(&reg->ispfx00.req_q_in, req->ring_index);

			RD_REG_DWORD_RELAXED(&reg->ispfx00.req_q_in);

			wrt_reg_dword(&reg->ispfx00.req_q_in, req->ring_index);

			rd_reg_dword_relaxed(&reg->ispfx00.req_q_in);

			QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);

		} else if (IS_FWI2_CAPABLE(ha)) {

			WRT_REG_DWORD(&reg->isp24.req_q_in, req->ring_index);

			RD_REG_DWORD_RELAXED(&reg->isp24.req_q_in);

			wrt_reg_dword(&reg->isp24.req_q_in, req->ring_index);

			rd_reg_dword_relaxed(&reg->isp24.req_q_in);

		} else {

			WRT_REG_WORD(ISP_REQ_Q_IN(ha, &reg->isp),

			wrt_reg_word(ISP_REQ_Q_IN(ha, &reg->isp),

				req->ring_index);

			RD_REG_WORD_RELAXED(ISP_REQ_Q_IN(ha, &reg->isp));

			rd_reg_word_relaxed(ISP_REQ_Q_IN(ha, &reg->isp));

		}

	}

}
@@ -1637,7 +1637,7 @@ qla24xx_start_scsi(srb_t *sp) 
	req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);

	if (req->cnt < (req_cnt + 2)) {

		cnt = IS_SHADOW_REG_CAPABLE(ha) ? *req->out_ptr :

		    RD_REG_DWORD_RELAXED(req->req_q_out);

		    rd_reg_dword_relaxed(req->req_q_out);

		if (req->ring_index < cnt)

			req->cnt = cnt - req->ring_index;

		else
@@ -1698,7 +1698,7 @@ qla24xx_start_scsi(srb_t *sp) 
	sp->flags |= SRB_DMA_VALID;



	/* Set chip new ring index. */

	WRT_REG_DWORD(req->req_q_in, req->ring_index);

	wrt_reg_dword(req->req_q_in, req->ring_index);



	spin_unlock_irqrestore(&ha->hardware_lock, flags);

	return QLA_SUCCESS;
@@ -1822,7 +1822,7 @@ qla24xx_dif_start_scsi(srb_t *sp) 
	tot_dsds += nseg;

	if (req->cnt < (req_cnt + 2)) {

		cnt = IS_SHADOW_REG_CAPABLE(ha) ? *req->out_ptr :

		    RD_REG_DWORD_RELAXED(req->req_q_out);

		    rd_reg_dword_relaxed(req->req_q_out);

		if (req->ring_index < cnt)

			req->cnt = cnt - req->ring_index;

		else
@@ -1881,7 +1881,7 @@ qla24xx_dif_start_scsi(srb_t *sp) 
		req->ring_ptr++;



	/* Set chip new ring index. */

	WRT_REG_DWORD(req->req_q_in, req->ring_index);

	wrt_reg_dword(req->req_q_in, req->ring_index);



	spin_unlock_irqrestore(&ha->hardware_lock, flags);
@@ -1957,7 +1957,7 @@ qla2xxx_start_scsi_mq(srb_t *sp) 
	req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);

	if (req->cnt < (req_cnt + 2)) {

		cnt = IS_SHADOW_REG_CAPABLE(ha) ? *req->out_ptr :

		    RD_REG_DWORD_RELAXED(req->req_q_out);

		    rd_reg_dword_relaxed(req->req_q_out);

		if (req->ring_index < cnt)

			req->cnt = cnt - req->ring_index;

		else
@@ -2018,7 +2018,7 @@ qla2xxx_start_scsi_mq(srb_t *sp) 
	sp->flags |= SRB_DMA_VALID;



	/* Set chip new ring index. */

	WRT_REG_DWORD(req->req_q_in, req->ring_index);

	wrt_reg_dword(req->req_q_in, req->ring_index);



	spin_unlock_irqrestore(&qpair->qp_lock, flags);

	return QLA_SUCCESS;
@@ -2157,7 +2157,7 @@ qla2xxx_dif_start_scsi_mq(srb_t *sp) 
	tot_dsds += nseg;

	if (req->cnt < (req_cnt + 2)) {

		cnt = IS_SHADOW_REG_CAPABLE(ha) ? *req->out_ptr :

		    RD_REG_DWORD_RELAXED(req->req_q_out);

		    rd_reg_dword_relaxed(req->req_q_out);

		if (req->ring_index < cnt)

			req->cnt = cnt - req->ring_index;

		else
@@ -2214,7 +2214,7 @@ qla2xxx_dif_start_scsi_mq(srb_t *sp) 
		req->ring_ptr++;



	/* Set chip new ring index. */

	WRT_REG_DWORD(req->req_q_in, req->ring_index);

	wrt_reg_dword(req->req_q_in, req->ring_index);



	/* Manage unprocessed RIO/ZIO commands in response queue. */

	if (vha->flags.process_response_queue &&
@@ -2266,13 +2266,13 @@ __qla2x00_alloc_iocbs(struct qla_qpair *qpair, srb_t *sp) 
			cnt = *req->out_ptr;

		else if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||

		    IS_QLA28XX(ha))

			cnt = RD_REG_DWORD(&reg->isp25mq.req_q_out);

			cnt = rd_reg_dword(&reg->isp25mq.req_q_out);

		else if (IS_P3P_TYPE(ha))

			cnt = RD_REG_DWORD(reg->isp82.req_q_out);

			cnt = rd_reg_dword(reg->isp82.req_q_out);

		else if (IS_FWI2_CAPABLE(ha))

			cnt = RD_REG_DWORD(&reg->isp24.req_q_out);

			cnt = rd_reg_dword(&reg->isp24.req_q_out);

		else if (IS_QLAFX00(ha))

			cnt = RD_REG_DWORD(&reg->ispfx00.req_q_out);

			cnt = rd_reg_dword(&reg->ispfx00.req_q_out);

		else

			cnt = qla2x00_debounce_register(

			    ISP_REQ_Q_OUT(ha, &reg->isp));
@@ -2305,8 +2305,8 @@ __qla2x00_alloc_iocbs(struct qla_qpair *qpair, srb_t *sp) 
	pkt = req->ring_ptr;

	memset(pkt, 0, REQUEST_ENTRY_SIZE);

	if (IS_QLAFX00(ha)) {

		WRT_REG_BYTE((void __iomem *)&pkt->entry_count, req_cnt);

		WRT_REG_WORD((void __iomem *)&pkt->handle, handle);

		wrt_reg_byte((void __iomem *)&pkt->entry_count, req_cnt);

		wrt_reg_word((void __iomem *)&pkt->handle, handle);

	} else {

		pkt->entry_count = req_cnt;

		pkt->handle = handle;
@@ -3310,7 +3310,7 @@ sufficient_dsds: 
		req_cnt = 1;



		if (req->cnt < (req_cnt + 2)) {

			cnt = (uint16_t)RD_REG_DWORD_RELAXED(

			cnt = (uint16_t)rd_reg_dword_relaxed(

				&reg->req_q_out[0]);

			if (req->ring_index < cnt)

				req->cnt = cnt - req->ring_index;
@@ -3419,7 +3419,7 @@ sufficient_dsds: 


		req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);

		if (req->cnt < (req_cnt + 2)) {

			cnt = (uint16_t)RD_REG_DWORD_RELAXED(

			cnt = (uint16_t)rd_reg_dword_relaxed(

			    &reg->req_q_out[0]);

			if (req->ring_index < cnt)

				req->cnt = cnt - req->ring_index;
@@ -3495,10 +3495,10 @@ sufficient_dsds: 
	if (ql2xdbwr)

		qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr, dbval);

	else {

		WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);

		wrt_reg_dword(ha->nxdb_wr_ptr, dbval);

		wmb();

		while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {

			WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);

		while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) {

			wrt_reg_dword(ha->nxdb_wr_ptr, dbval);

			wmb();

		}

	}
@@ -3894,7 +3894,7 @@ qla2x00_start_bidir(srb_t *sp, struct scsi_qla_host *vha, uint32_t tot_dsds) 
	/* Check for room on request queue. */

	if (req->cnt < req_cnt + 2) {

		cnt = IS_SHADOW_REG_CAPABLE(ha) ? *req->out_ptr :

		    RD_REG_DWORD_RELAXED(req->req_q_out);

		    rd_reg_dword_relaxed(req->req_q_out);

		if  (req->ring_index < cnt)

			req->cnt = cnt - req->ring_index;

		else

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