Commit 04300171 authored Jun 07, 2019 by David Galiffi Committed by Alex Deucher Jul 18, 2019

drm/amd/display: Incorrect Read Interval Time For CR Sequence



[WHY]
TRAINING_AUX_RD_INTERVAL (DPCD 000Eh) modifies the read interval
for the EQ training sequence. CR read interval should remain 100 us.
Currently, the CR interval is also being modified.

[HOW]
lt_settings->cr_pattern_time should always be 100 us.

Signed-off-by: David Galiffi <david.galiffi@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 0b6cbbd5

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -1035,7 +1035,7 @@ static void initialize_training_settings(
		if (link->preferred_training_settings.cr_pattern_time != NULL)
		lt_settings->cr_pattern_time = *link->preferred_training_settings.cr_pattern_time;
		else
		lt_settings->cr_pattern_time = get_training_aux_rd_interval(link, 100);
		lt_settings->cr_pattern_time = 100;

		if (link->preferred_training_settings.eq_pattern_time != NULL)
		lt_settings->eq_pattern_time = *link->preferred_training_settings.eq_pattern_time;

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