Commit 041cadca authored by Mark Salter's avatar Mark Salter
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C6X: devicetree support 



This is the basic devicetree support for C6X. Currently, four boards are
supported. Each one uses a different SoC part. Two of the four supported
SoCs are multicore. One with 3 cores and the other with 6 cores. There is
no coherency between the core-level caches, so SMP is not an option. It is
possible to run separate kernel instances on the various cores. There is
currently no C6X bootloader support for device trees so we build in the DTB
for now.

There are some interesting twists to the hardware which are of note for device
tree support. Each core has its own interrupt controller which is controlled
by special purpose core registers. This core controller provides 12 general
purpose prioritized interrupt sources. Each core is contained within a
hardware "module" which provides L1 and L2 caches, power control, and another
interrupt controller which cascades into the core interrupt controller. These
core module functions are controlled by memory mapped registers. The addresses
for these registers are the same for each core. That is, when coreN accesses
a module-level MMIO register at a given address, it accesses the register for
coreN even though other cores would use the same address to access the register
in the module containing those cores. Other hardware modules (timers, enet, etc)
which are memory mapped can be accessed by all cores.

The timers need some further explanation for multicore SoCs. Even though all
timer control registers are visible to all cores, interrupt routing or other
considerations may make a given timer more suitable for use by a core than
some other timer. Because of this and the desire to have the same image run
on more than one core, the timer nodes have a "ti,core-mask" property which
is used by the driver to scan for a suitable timer to use.

Signed-off-by: default avatarMark Salter <msalter@redhat.com>
Signed-off-by: default avatarAurelien Jacquiot <a-jacquiot@ti.com>
Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
parent c1a144d7

Documentation/devicetree/bindings/c6x/clocks.txt

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C6X PLL Clock Controllers

-------------------------



This is a first-cut support for the SoC clock controllers. This is still

under development and will probably change as the common device tree

clock support is added to the kernel.



Required properties:



- compatible: "ti,c64x+pll"

    May also have SoC-specific value to support SoC-specific initialization

    in the driver. One of:

        "ti,c6455-pll"

        "ti,c6457-pll"

        "ti,c6472-pll"

        "ti,c6474-pll"



- reg: base address and size of register area

- clock-frequency: input clock frequency in hz





Optional properties:



- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode



- ti,c64x+pll-reset-delay:  CPU cycles to delay after PLL reset



- ti,c64x+pll-lock-delay:   CPU cycles to delay after PLL frequency change



Example:



	clock-controller@29a0000 {

		compatible = "ti,c6472-pll", "ti,c64x+pll";

		reg = <0x029a0000 0x200>;

		clock-frequency = <25000000>;



		ti,c64x+pll-bypass-delay = <200>;

		ti,c64x+pll-reset-delay = <12000>;

		ti,c64x+pll-lock-delay = <80000>;

	};

Documentation/devicetree/bindings/c6x/dscr.txt

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Device State Configuration Registers

------------------------------------



TI C6X SoCs contain a region of miscellaneous registers which provide various

function for SoC control or status. Details vary considerably among from SoC

to SoC with no two being alike.



In general, the Device State Configuraion Registers (DSCR) will provide one or

more configuration registers often protected by a lock register where one or

more key values must be written to a lock register in order to unlock the

configuration register for writes. These configuration register may be used to

enable (and disable in some cases) SoC pin drivers, select peripheral clock

sources (internal or pin), etc. In some cases, a configuration register is

write once or the individual bits are write once. In addition to device config,

the DSCR block may provide registers which which are used to reset peripherals,

provide device ID information, provide ethernet MAC addresses, as well as other

miscellaneous functions.



For device state control (enable/disable), each device control is assigned an

id which is used by individual device drivers to control the state as needed.



Required properties:



- compatible: must be "ti,c64x+dscr"

- reg: register area base and size



Optional properties:



  NOTE: These are optional in that not all SoCs will have all properties. For

        SoCs which do support a given property, leaving the property out of the

        device tree will result in reduced functionality or possibly driver

        failure.



- ti,dscr-devstat

    offset of the devstat register



- ti,dscr-silicon-rev

    offset, start bit, and bitsize of silicon revision field



- ti,dscr-rmii-resets

    offset and bitmask of RMII reset field. May have multiple tuples if more

    than one ethernet port is available.



- ti,dscr-locked-regs

    possibly multiple tuples describing registers which are write protected by

    a lock register. Each tuple consists of the register offset, lock register

    offsset, and the key value used to unlock the register.



- ti,dscr-kick-regs

    offset and key values of two "kick" registers used to write protect other

    registers in DSCR. On SoCs using kick registers, the first key must be

    written to the first kick register and the second key must be written to

    the second register before other registers in the area are write-enabled.



- ti,dscr-mac-fuse-regs

    MAC addresses are contained in two registers. Each element of a MAC address

    is contained in a single byte. This property has two tuples. Each tuple has

    a register offset and four cells representing bytes in the register from

    most significant to least. The value of these four cells is the MAC byte

    index (1-6) of the byte within the register. A value of 0 means the byte

    is unused in the MAC address.



- ti,dscr-devstate-ctl-regs

    This property describes the bitfields used to control the state of devices.

    Each tuple describes a range of identical bitfields used to control one or

    more devices (one bitfield per device). The layout of each tuple is:



        start_id num_ids reg enable disable start_bit nbits



    Where:

        start_id is device id for the first device control in the range

        num_ids is the number of device controls in the range

        reg is the offset of the register holding the control bits

        enable is the value to enable a device

        disable is the value to disable a device (0xffffffff if cannot disable)

        start_bit is the bit number of the first bit in the range

        nbits is the number of bits per device control



- ti,dscr-devstate-stat-regs

    This property describes the bitfields used to provide device state status

    for device states controlled by the DSCR. Each tuple describes a range of

    identical bitfields used to provide status for one or more devices (one

    bitfield per device). The layout of each tuple is:



        start_id num_ids reg enable disable start_bit nbits



    Where:

        start_id is device id for the first device status in the range

        num_ids is the number of devices covered by the range

        reg is the offset of the register holding the status bits

        enable is the value indicating device is enabled

        disable is the value indicating device is disabled

        start_bit is the bit number of the first bit in the range

        nbits is the number of bits per device status



- ti,dscr-privperm

    Offset and default value for register used to set access privilege for

    some SoC devices.





Example:



	device-state-config-regs@2a80000 {

		compatible = "ti,c64x+dscr";

		reg = <0x02a80000 0x41000>;



		ti,dscr-devstat = <0>;

		ti,dscr-silicon-rev = <8 28 0xf>;

		ti,dscr-rmii-resets = <0x40020 0x00040000>;



		ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;

		ti,dscr-devstate-ctl-regs =

			 <0 12 0x40008 1 0  0  2

			  12 1 0x40008 3 0 30  2

			  13 2 0x4002c 1 0xffffffff 0 1>;

		ti,dscr-devstate-stat-regs =

			<0 10 0x40014 1 0  0  3

			 10 2 0x40018 1 0  0  3>;



		ti,dscr-mac-fuse-regs = <0x700 1 2 3 4

					 0x704 5 6 0 0>;



		ti,dscr-privperm = <0x41c 0xaaaaaaaa>;



		ti,dscr-kick-regs = <0x38 0x83E70B13

				     0x3c 0x95A4F1E0>;

	};

Documentation/devicetree/bindings/c6x/emifa.txt

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External Memory Interface

-------------------------



The emifa node describes a simple external bus controller found on some C6X

SoCs. This interface provides external busses with a number of chip selects.



Required properties:



- compatible: must be "ti,c64x+emifa", "simple-bus"

- reg: register area base and size

- #address-cells: must be 2 (chip-select + offset)

- #size-cells: must be 1

- ranges: mapping from EMIFA space to parent space





Optional properties:



- ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR



- ti,emifa-burst-priority:

      Number of memory transfers after which the EMIF will elevate the priority

      of the oldest command in the command FIFO. Setting this field to 255

      disables this feature, thereby allowing old commands to stay in the FIFO

      indefinitely.



- ti,emifa-ce-config:

      Configuration values for each of the supported chip selects.



Example:



	emifa@70000000 {

		compatible = "ti,c64x+emifa", "simple-bus";

		#address-cells = <2>;

		#size-cells = <1>;

		reg = <0x70000000 0x100>;

		ranges = <0x2 0x0 0xa0000000 0x00000008

		          0x3 0x0 0xb0000000 0x00400000

			  0x4 0x0 0xc0000000 0x10000000

			  0x5 0x0 0xD0000000 0x10000000>;



		ti,dscr-dev-enable = <13>;

		ti,emifa-burst-priority = <255>;

		ti,emifa-ce-config = <0x00240120

				      0x00240120

				      0x00240122

				      0x00240122>;



		flash@3,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "cfi-flash";

			reg = <0x3 0x0 0x400000>;

			bank-width = <1>;

			device-width = <1>;

			partition@0 {

				reg = <0x0 0x400000>;

				label = "NOR";

			};

		};

	};



This shows a flash chip attached to chip select 3.

Documentation/devicetree/bindings/c6x/interrupt.txt

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C6X Interrupt Chips

-------------------



* C64X+ Core Interrupt Controller



  The core interrupt controller provides 16 prioritized interrupts to the

  C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.

  Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt

  sources coming from outside the core.



  Required properties:

  --------------------

  - compatible: Should be "ti,c64x+core-pic";

  - #interrupt-cells: <1>



  Interrupt Specifier Definition

  ------------------------------

  Single cell specifying the core interrupt priority level (4-15) where

  4 is highest priority and 15 is lowest priority.



  Example

  -------

  core_pic: interrupt-controller@0 {

	interrupt-controller;

	#interrupt-cells = <1>;

	compatible = "ti,c64x+core-pic";

  };







* C64x+ Megamodule Interrupt Controller



  The megamodule PIC consists of four interrupt mupliplexers each of which

  combine up to 32 interrupt inputs into a single interrupt output which

  may be cascaded into the core interrupt controller. The megamodule PIC

  has a total of 12 outputs cascading into the core interrupt controller.

  One for each core interrupt priority level. In addition to the combined

  interrupt sources, individual megamodule interrupts may be cascaded to

  the core interrupt controller. When an individual interrupt is cascaded,

  it is no longer handled through a megamodule interrupt combiner and is

  considered to have the core interrupt controller as the parent.



  Required properties:

  --------------------

  - compatible: "ti,c64x+megamod-pic"

  - interrupt-controller

  - #interrupt-cells: <1>

  - reg: base address and size of register area

  - interrupt-parent: must be core interrupt controller

  - interrupts: This should have four cells; one for each interrupt combiner.

                The cells contain the core priority interrupt to which the

                corresponding combiner output is wired.



  Optional properties:

  --------------------

  - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core

                             priority interrupts. The first cell corresponds to

                             core priority 4 and the last cell corresponds to

                             core priority 15. The value of each cell is the

                             megamodule interrupt source which is MUXed to

                             the core interrupt corresponding to the cell

                             position. Allowed values are 4 - 127. Mapping for

                             interrupts 0 - 3 (combined interrupt sources) are

                             ignored.



  Interrupt Specifier Definition

  ------------------------------

  Single cell specifying the megamodule interrupt source (4-127). Note that

  interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will

  use the core interrupt controller as their parent and the specifier will

  be the core priority level, not the megamodule interrupt number.



  Examples

  --------

  megamod_pic: interrupt-controller@1800000 {

	compatible = "ti,c64x+megamod-pic";

	interrupt-controller;

	#interrupt-cells = <1>;

	reg = <0x1800000 0x1000>;

	interrupt-parent = <&core_pic>;

	interrupts = < 12 13 14 15 >;

  };



  This is a minimal example where all individual interrupts go through a

  combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped

  to interrupt 13, etc.





  megamod_pic: interrupt-controller@1800000 {

	compatible = "ti,c64x+megamod-pic";

	interrupt-controller;

	#interrupt-cells = <1>;

	reg = <0x1800000 0x1000>;

	interrupt-parent = <&core_pic>;

	interrupts = < 12 13 14 15 >;

	ti,c64x+megamod-pic-mux = <  0  0  0  0

                                    32  0  0  0

                                     0  0  0  0 >;

  };



  This the same as the first example except that megamodule interrupt 32 is

  mapped directly to core priority interrupt 8. The node using this interrupt

  must set the core controller as its interrupt parent and use 8 in the

  interrupt specifier value.

Documentation/devicetree/bindings/c6x/soc.txt

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C6X System-on-Chip

------------------



Required properties:



- compatible: "simple-bus"

- #address-cells: must be 1

- #size-cells: must be 1

- ranges



Optional properties:



- model: specific SoC model



- nodes for IP blocks within SoC





Example:



	soc {

		compatible = "simple-bus";

		model = "tms320c6455";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;



		...

	};

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