drm/i915: Set up PIPE_MISC truncate bit on tgl+ (041be481) · Commits · 戴 / test

Looks like the pipe rounding mode bit has moved from PIPE_CHICKEN to PIPE_MISC on tgl. Frob the new location. Bspec does still document the old bits as well, so I left the code for them as is until we get clarification from the hw folks on whether the old bits still do something useful. Signed-off-by:

Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200226163054.9509-1-ville.syrjala@linux.intel.com Reviewed-by:

José Roberto de Souza <jose.souza@intel.com>

drivers/gpu/drm/i915/display/intel_display.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -10138,6 +10138,9 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
		BIT(PLANE_CURSOR))) == 0)
		val \|= PIPEMISC_HDR_MODE_PRECISION;

		if (INTEL_GEN(dev_priv) >= 12)
		val \|= PIPEMISC_PIXEL_ROUNDING_TRUNC;

		intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
		}

drivers/gpu/drm/i915/i915_reg.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -5879,6 +5879,7 @@ enum {
		#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
		#define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */
		#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
		#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
		#define PIPEMISC_DITHER_BPC_MASK (7 << 5)
		#define PIPEMISC_DITHER_8_BPC (0 << 5)
		#define PIPEMISC_DITHER_10_BPC (1 << 5)

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