Commit 03d6e3aa authored by James Zhu's avatar James Zhu Committed by Alex Deucher
Browse files

drm/amdgpu:Add DPG mode read/write macro 



Some registers read/write needs program through SDRAM pool under
DPG mode.

Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f28ff062

drivers/gpu/drm/amd/amdgpu/soc15_common.h

+20 −0
Original line number Diff line number Diff line
@@ -64,6 +64,26 @@ 
		}						\

	} while (0)



#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) 	\

		({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \

			WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL,	\

				UVD_DPG_LMA_CTL__MASK_EN_MASK |				\

				((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \

				<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \

				(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));	\

			RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); })



#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel)	\

	do {							\

		WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value);	\

		WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask);		\

		WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL,	\

			UVD_DPG_LMA_CTL__READ_WRITE_MASK |	\

			((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \

			<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) |	\

			(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \

	} while (0)



#endif

CRA Git | Maintained and supported by SUSTech CRA and CCSE