Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm (03a6c259) · Commits · 戴 / test

Documentation/virtual/kvm/api.txt

+28 −12

Original line number	Diff line number	Diff line
		@@ -123,14 +123,15 @@ memory layout to fit in user mode), check KVM_CAP_MIPS_VZ and use the
		flag KVM_VM_MIPS_VZ.


		4.3 KVM_GET_MSR_INDEX_LIST
		4.3 KVM_GET_MSR_INDEX_LIST, KVM_GET_MSR_FEATURE_INDEX_LIST

		Capability: basic
		Capability: basic, KVM_CAP_GET_MSR_FEATURES for KVM_GET_MSR_FEATURE_INDEX_LIST
		Architectures: x86
		Type: system
		Type: system ioctl
		Parameters: struct kvm_msr_list (in/out)
		Returns: 0 on success; -1 on error
		Errors:
		EFAULT: the msr index list cannot be read from or written to
		E2BIG: the msr index list is to be to fit in the array specified by
		the user.

		@@ -139,16 +140,23 @@ struct kvm_msr_list {
		__u32 indices[0];
		};

		This ioctl returns the guest msrs that are supported. The list varies
		by kvm version and host processor, but does not change otherwise. The
		user fills in the size of the indices array in nmsrs, and in return
		kvm adjusts nmsrs to reflect the actual number of msrs and fills in
		the indices array with their numbers.
		The user fills in the size of the indices array in nmsrs, and in return
		kvm adjusts nmsrs to reflect the actual number of msrs and fills in the
		indices array with their numbers.

		KVM_GET_MSR_INDEX_LIST returns the guest msrs that are supported. The list
		varies by kvm version and host processor, but does not change otherwise.

		Note: if kvm indicates supports MCE (KVM_CAP_MCE), then the MCE bank MSRs are
		not returned in the MSR list, as different vcpus can have a different number
		of banks, as set via the KVM_X86_SETUP_MCE ioctl.

		KVM_GET_MSR_FEATURE_INDEX_LIST returns the list of MSRs that can be passed
		to the KVM_GET_MSRS system ioctl. This lets userspace probe host capabilities
		and processor features that are exposed via MSRs (e.g., VMX capabilities).
		This list also varies by kvm version and host processor, but does not change
		otherwise.


		4.4 KVM_CHECK_EXTENSION

		@@ -475,14 +483,22 @@ Support for this has been removed. Use KVM_SET_GUEST_DEBUG instead.

		4.18 KVM_GET_MSRS

		Capability: basic
		Capability: basic (vcpu), KVM_CAP_GET_MSR_FEATURES (system)
		Architectures: x86
		Type: vcpu ioctl
		Type: system ioctl, vcpu ioctl
		Parameters: struct kvm_msrs (in/out)
		Returns: 0 on success, -1 on error
		Returns: number of msrs successfully returned;
		-1 on error

		When used as a system ioctl:
		Reads the values of MSR-based features that are available for the VM. This
		is similar to KVM_GET_SUPPORTED_CPUID, but it returns MSR indices and values.
		The list of msr-based features can be obtained using KVM_GET_MSR_FEATURE_INDEX_LIST
		in a system ioctl.

		When used as a vcpu ioctl:
		Reads model-specific registers from the vcpu. Supported msr indices can
		be obtained using KVM_GET_MSR_INDEX_LIST.
		be obtained using KVM_GET_MSR_INDEX_LIST in a system ioctl.

		struct kvm_msrs {
		__u32 nmsrs; /* number of msrs in entries */

arch/x86/include/asm/kvm_host.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -507,6 +507,7 @@ struct kvm_vcpu_arch {
		u64 smi_count;
		bool tpr_access_reporting;
		u64 ia32_xss;
		u64 microcode_version;

		/*
		* Paging state of the vcpu
		@@ -1095,6 +1096,8 @@ struct kvm_x86_ops {
		int (mem_enc_op)(struct kvm kvm, void __user *argp);
		int (mem_enc_reg_region)(struct kvm kvm, struct kvm_enc_region *argp);
		int (mem_enc_unreg_region)(struct kvm kvm, struct kvm_enc_region *argp);

		int (get_msr_feature)(struct kvm_msr_entry entry);
		};

		struct kvm_arch_async_pf {

arch/x86/kvm/lapic.c

+4 −6

Original line number	Diff line number	Diff line
		@@ -2002,14 +2002,13 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)

		void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
		{
		struct kvm_lapic *apic;
		struct kvm_lapic *apic = vcpu->arch.apic;
		int i;

		apic_debug("%s\n", __func__);
		if (!apic)
		return;

		ASSERT(vcpu);
		apic = vcpu->arch.apic;
		ASSERT(apic != NULL);
		apic_debug("%s\n", __func__);

		/* Stop the timer in case it's a reset to an active apic */
		hrtimer_cancel(&apic->lapic_timer.timer);
		@@ -2568,7 +2567,6 @@ void kvm_apic_accept_events(struct kvm_vcpu *vcpu)

		pe = xchg(&apic->pending_events, 0);
		if (test_bit(KVM_APIC_INIT, &pe)) {
		kvm_lapic_reset(vcpu, true);
		kvm_vcpu_reset(vcpu, true);
		if (kvm_vcpu_is_bsp(apic->vcpu))
		vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;

arch/x86/kvm/svm.c

+41 −3

Original line number	Diff line number	Diff line
		@@ -179,6 +179,8 @@ struct vcpu_svm {
		uint64_t sysenter_eip;
		uint64_t tsc_aux;

		u64 msr_decfg;

		u64 next_rip;

		u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
		@@ -1906,6 +1908,7 @@ static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
		u32 dummy;
		u32 eax = 1;

		vcpu->arch.microcode_version = 0x01000065;
		svm->spec_ctrl = 0;

		if (!init_event) {
		@@ -3870,6 +3873,22 @@ static int cr8_write_interception(struct vcpu_svm *svm)
		return 0;
		}

		static int svm_get_msr_feature(struct kvm_msr_entry *msr)
		{
		msr->data = 0;

		switch (msr->index) {
		case MSR_F10H_DECFG:
		if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
		msr->data \|= MSR_F10H_DECFG_LFENCE_SERIALIZE;
		break;
		default:
		return 1;
		}

		return 0;
		}

		static int svm_get_msr(struct kvm_vcpu vcpu, struct msr_data msr_info)
		{
		struct vcpu_svm *svm = to_svm(vcpu);
		@@ -3945,9 +3964,6 @@ static int svm_get_msr(struct kvm_vcpu vcpu, struct msr_data msr_info)

		msr_info->data = svm->spec_ctrl;
		break;
		case MSR_IA32_UCODE_REV:
		msr_info->data = 0x01000065;
		break;
		case MSR_F15H_IC_CFG: {

		int family, model;
		@@ -3965,6 +3981,9 @@ static int svm_get_msr(struct kvm_vcpu vcpu, struct msr_data msr_info)
		msr_info->data = 0x1E;
		}
		break;
		case MSR_F10H_DECFG:
		msr_info->data = svm->msr_decfg;
		break;
		default:
		return kvm_get_msr_common(vcpu, msr_info);
		}
		@@ -4143,6 +4162,24 @@ static int svm_set_msr(struct kvm_vcpu vcpu, struct msr_data msr)
		case MSR_VM_IGNNE:
		vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
		break;
		case MSR_F10H_DECFG: {
		struct kvm_msr_entry msr_entry;

		msr_entry.index = msr->index;
		if (svm_get_msr_feature(&msr_entry))
		return 1;

		/* Check the supported bits */
		if (data & ~msr_entry.data)
		return 1;

		/* Don't allow the guest to change a bit, #GP */
		if (!msr->host_initiated && (data ^ msr_entry.data))
		return 1;

		svm->msr_decfg = data;
		break;
		}
		case MSR_IA32_APICBASE:
		if (kvm_vcpu_apicv_active(vcpu))
		avic_update_vapic_bar(to_svm(vcpu), data);
		@@ -6833,6 +6870,7 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
		.vcpu_unblocking = svm_vcpu_unblocking,

		.update_bp_intercept = update_bp_intercept,
		.get_msr_feature = svm_get_msr_feature,
		.get_msr = svm_get_msr,
		.set_msr = svm_set_msr,
		.get_segment_base = svm_get_segment_base,

arch/x86/kvm/vmx.c

+7 −0

Original line number	Diff line number	Diff line
		@@ -3227,6 +3227,11 @@ static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
		return !(val & ~valid_bits);
		}

		static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
		{
		return 1;
		}

		/*
		* Reads an msr value (of 'msr_index') into 'pdata'.
		* Returns 0 on success, non-0 otherwise.
		@@ -5767,6 +5772,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
		vmx->rmode.vm86_active = 0;
		vmx->spec_ctrl = 0;

		vcpu->arch.microcode_version = 0x100000000ULL;
		vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
		kvm_set_cr8(vcpu, 0);

		@@ -12297,6 +12303,7 @@ static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
		.vcpu_put = vmx_vcpu_put,

		.update_bp_intercept = update_exception_bitmap,
		.get_msr_feature = vmx_get_msr_feature,
		.get_msr = vmx_get_msr,
		.set_msr = vmx_set_msr,
		.get_segment_base = vmx_get_segment_base,

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