Commit 03208cc6 authored by Tony Lindgren's avatar Tony Lindgren Committed by Michael Turquette
Browse files

clk: ti: Fix FAPLL parent enable bit handling 



Commit 163152cb ("clk: ti: Add support for FAPLL on dm816x")
added basic support for the FAPLL on dm818x, but has a bug for the
parent PLL enable bit. The FAPLL_MAIN_PLLEN is defined as BIT(3)
but the code is doing a shift on it.

This means the parent PLL won't get disabled even if all it's child
synthesizers are disabled.

Reported-by: default avatarDan Carpenter <dan.carpenter@oracle.com>
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
parent c517d838

drivers/clk/ti/fapll.c

+3 −3
Original line number Diff line number Diff line
@@ -84,7 +84,7 @@ static int ti_fapll_enable(struct clk_hw *hw) 
	struct fapll_data *fd = to_fapll(hw);

	u32 v = readl_relaxed(fd->base);



	v |= (1 << FAPLL_MAIN_PLLEN);

	v |= FAPLL_MAIN_PLLEN;

	writel_relaxed(v, fd->base);



	return 0;
@@ -95,7 +95,7 @@ static void ti_fapll_disable(struct clk_hw *hw) 
	struct fapll_data *fd = to_fapll(hw);

	u32 v = readl_relaxed(fd->base);



	v &= ~(1 << FAPLL_MAIN_PLLEN);

	v &= ~FAPLL_MAIN_PLLEN;

	writel_relaxed(v, fd->base);

}
@@ -104,7 +104,7 @@ static int ti_fapll_is_enabled(struct clk_hw *hw) 
	struct fapll_data *fd = to_fapll(hw);

	u32 v = readl_relaxed(fd->base);



	return v & (1 << FAPLL_MAIN_PLLEN);

	return v & FAPLL_MAIN_PLLEN;

}



static unsigned long ti_fapll_recalc_rate(struct clk_hw *hw,

CRA Git | Maintained and supported by SUSTech CRA and CCSE