Commit 02f7f61e authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-mvpp2-improve-the-interrupt-usage' 



Antoine Tenart says:

====================
net: mvpp2: improve the interrupt usage

This series aims to improve the interrupts descriptions and usage in the
Marvell PPv2 driver.

- Before the series interrupts were named after their s/w usage,
  which in fact can be configured. The series rename all those
  interrupts and add a description of the ones left over.

- In PPv2 the interrupts are mapped to vectors. Those vectors were
  directly mapped to a given CPU, and per-cpu accesses were done. While
  this worked on our cases, the registers accesses mapped to the vectors
  are not actually linked to a given CPU. They instead are linked to
  what is called a "s/w thread". The series modify this so that the s/w
  threads are used instead of the CPU numbers, by adding an indirection.
  This means we now can have systems with more CPUs than s/w threads.

This is based on today's net-next, and was tested on various boards
using both versions of the PPv2 engine.

Two more patches will be coming, to update the device trees describing a
PPv2 engine. The patches are ready, but will go through a different
tree. I'll send them once this series will be accepted. This is not an
issue as the PPv2 driver keeps the dt bindings backward compatibility.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents f543305d 1068549c

Documentation/devicetree/bindings/net/marvell-pp2.txt

+31 −14
Original line number Diff line number Diff line
@@ -31,7 +31,7 @@ required. 


Required properties (port):



- interrupts: interrupt for the port

- interrupts: interrupt(s) for the port

- port-id: ID of the port from the MAC point of view

- gop-port-id: only for marvell,armada-7k-pp2, ID of the port from the

  GOP (Group Of Ports) point of view. This ID is used to index the
@@ -43,10 +43,12 @@ Optional properties (port): 
- marvell,loopback: port is loopback mode

- phy: a phandle to a phy node defining the PHY address (as the reg

  property, a single integer).

- interrupt-names: if more than a single interrupt for rx is given, must

                   be the name associated to the interrupts listed. Valid

                   names are: "tx-cpu0", "tx-cpu1", "tx-cpu2", "tx-cpu3",

		   "rx-shared", "link".

- interrupt-names: if more than a single interrupt for is given, must be the

                   name associated to the interrupts listed. Valid names are:

                   "hifX", with X in [0..8], and "link". The names "tx-cpu0",

                   "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported

                   for backward compatibility but shouldn't be used for new

                   additions.

- marvell,system-controller: a phandle to the system controller.



Example for marvell,armada-375-pp2:
@@ -89,9 +91,14 @@ cpm_ethernet: ethernet@0 { 
			     <ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",

				  "tx-cpu3", "rx-shared";

			     <ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 59 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 63 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 67 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 71 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",

				  "hif5", "hif6", "hif7", "hif8", "link";

		port-id = <0>;

		gop-port-id = <0>;

	};
@@ -101,9 +108,14 @@ cpm_ethernet: ethernet@0 { 
			     <ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",

				  "tx-cpu3", "rx-shared";

			     <ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 60 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 64 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 68 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 72 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",

				  "hif5", "hif6", "hif7", "hif8", "link";

		port-id = <1>;

		gop-port-id = <2>;

	};
@@ -113,9 +125,14 @@ cpm_ethernet: ethernet@0 { 
			     <ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",

				  "tx-cpu3", "rx-shared";

			     <ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 61 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 65 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 69 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 73 IRQ_TYPE_LEVEL_HIGH>,

			     <ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "hif0", "hif1", "hif2", "hif3", "hif4",

				  "hif5", "hif6", "hif7", "hif8", "link";

		port-id = <2>;

		gop-port-id = <3>;

	};

drivers/net/ethernet/marvell/mvpp2/mvpp2.h

+16 −11
Original line number Diff line number Diff line
@@ -253,7 +253,8 @@ 
#define     MVPP2_ISR_ENABLE_INTERRUPT(mask)	((mask) & 0xffff)

#define     MVPP2_ISR_DISABLE_INTERRUPT(mask)	(((mask) << 16) & 0xffff0000)

#define MVPP2_ISR_RX_TX_CAUSE_REG(port)		(0x5480 + 4 * (port))

#define     MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK	0xffff

#define     MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(version) \

					((version) == MVPP21 ? 0xffff : 0xff)

#define     MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK	0xff0000

#define     MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET	16

#define     MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK	BIT(24)
@@ -613,6 +614,7 @@ 


/* Port flags */

#define MVPP2_F_LOOPBACK		BIT(0)

#define MVPP2_F_DT_COMPAT		BIT(1)



/* Marvell tag types */

enum mvpp2_tag_type {
@@ -662,7 +664,7 @@ enum mvpp2_prs_l3_cast { 
#define MVPP21_ADDR_SPACE_SZ		0

#define MVPP22_ADDR_SPACE_SZ		SZ_64K



#define MVPP2_MAX_THREADS		8

#define MVPP2_MAX_THREADS		9

#define MVPP2_MAX_QVECS			MVPP2_MAX_THREADS



/* GMAC MIB Counters register definitions */
@@ -734,6 +736,11 @@ struct mvpp2 { 
	int port_count;

	struct mvpp2_port *port_list[MVPP2_MAX_PORTS];



	/* Number of Tx threads used */

	unsigned int nthreads;

	/* Map of threads needing locking */

	unsigned long lock_map;



	/* Aggregated TXQs */

	struct mvpp2_tx_queue *aggr_txqs;
@@ -823,6 +830,12 @@ struct mvpp2_port { 
	/* Per-CPU port control */

	struct mvpp2_port_pcpu __percpu *pcpu;



	/* Protect the BM refills and the Tx paths when a thread is used on more

	 * than a single CPU.

	 */

	spinlock_t bm_lock[MVPP2_MAX_THREADS];

	spinlock_t tx_lock[MVPP2_MAX_THREADS];



	/* Flags */

	unsigned long flags;
@@ -969,7 +982,7 @@ struct mvpp2_txq_pcpu_buf { 


/* Per-CPU Tx queue control */

struct mvpp2_txq_pcpu {

	int cpu;

	unsigned int thread;



	/* Number of Tx DMA descriptors in the descriptor ring */

	int size;
@@ -1095,14 +1108,6 @@ struct mvpp2_bm_pool { 
void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data);

u32 mvpp2_read(struct mvpp2 *priv, u32 offset);



u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset);



void mvpp2_percpu_write(struct mvpp2 *priv, int cpu, u32 offset, u32 data);

u32 mvpp2_percpu_read(struct mvpp2 *priv, int cpu, u32 offset);



void mvpp2_percpu_write_relaxed(struct mvpp2 *priv, int cpu, u32 offset,

				u32 data);



void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name);



void mvpp2_dbgfs_cleanup(struct mvpp2 *priv);

drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

+268 −163

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