arm64: cache: Merge cachetype.h into cache.h (02f7760e) · Commits · 戴 / test

arch/arm64/include/asm/cache.h

+30 −1

Original line number	Original line	Diff line number	Diff line
	@@ -16,7 +16,17 @@
	#ifndef __ASM_CACHE_H		#ifndef __ASM_CACHE_H
	#define __ASM_CACHE_H		#define __ASM_CACHE_H

	#include <asm/cachetype.h>		#include <asm/cputype.h>

			#define CTR_L1IP_SHIFT 14
			#define CTR_L1IP_MASK 3
			#define CTR_CWG_SHIFT 24
			#define CTR_CWG_MASK 15

			#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)

			#define ICACHE_POLICY_VIPT 2
			#define ICACHE_POLICY_PIPT 3

	#define L1_CACHE_SHIFT 7		#define L1_CACHE_SHIFT 7
	#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)		#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
	@@ -32,6 +42,25 @@

	#ifndef __ASSEMBLY__		#ifndef __ASSEMBLY__

			#include <linux/bitops.h>

			#define ICACHEF_ALIASING 0
			extern unsigned long __icache_flags;

			/*
			* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
			* permitted in the I-cache.
			*/
			static inline int icache_is_aliasing(void)
			{
			return test_bit(ICACHEF_ALIASING, &__icache_flags);
			}

			static inline u32 cache_type_cwg(void)
			{
			return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
			}

	#define __read_mostly __attribute__((__section__(".data..read_mostly")))		#define __read_mostly __attribute__((__section__(".data..read_mostly")))

	static inline int cache_line_size(void)		static inline int cache_line_size(void)

deleted100644 → 0

+0 −55

Original line number	Original line	Diff line number	Diff line
	/*
	* Copyright (C) 2012 ARM Ltd.
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 as
	* published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*
	* You should have received a copy of the GNU General Public License
	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	*/
	#ifndef __ASM_CACHETYPE_H
	#define __ASM_CACHETYPE_H

	#include <asm/cputype.h>

	#define CTR_L1IP_SHIFT 14
	#define CTR_L1IP_MASK 3
	#define CTR_CWG_SHIFT 24
	#define CTR_CWG_MASK 15

	#define ICACHE_POLICY_VIPT 2
	#define ICACHE_POLICY_PIPT 3

	#ifndef __ASSEMBLY__

	#include <linux/bitops.h>

	#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)

	#define ICACHEF_ALIASING 0

	extern unsigned long __icache_flags;

	/*
	* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
	* permitted in the I-cache.
	*/
	static inline int icache_is_aliasing(void)
	{
	return test_bit(ICACHEF_ALIASING, &__icache_flags);
	}

	static inline u32 cache_type_cwg(void)
	{
	return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
	}

	#endif /* __ASSEMBLY__ */

	#endif /* __ASM_CACHETYPE_H */

+1 −1

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -15,7 +15,7 @@
	* along with this program. If not, see <http://www.gnu.org/licenses/>.		* along with this program. If not, see <http://www.gnu.org/licenses/>.
	*/		*/
	#include <asm/arch_timer.h>		#include <asm/arch_timer.h>
	#include <asm/cachetype.h>		#include <asm/cache.h>
	#include <asm/cpu.h>		#include <asm/cpu.h>
	#include <asm/cputype.h>		#include <asm/cputype.h>
	#include <asm/cpufeature.h>		#include <asm/cpufeature.h>

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -22,7 +22,7 @@
	#include <linux/pagemap.h>		#include <linux/pagemap.h>

	#include <asm/cacheflush.h>		#include <asm/cacheflush.h>
	#include <asm/cachetype.h>		#include <asm/cache.h>
	#include <asm/tlbflush.h>		#include <asm/tlbflush.h>

	void sync_icache_aliases(void *kaddr, unsigned long len)		void sync_icache_aliases(void *kaddr, unsigned long len)