ARM: dts: sun8i: V3/V3s/S3/S3L: add Ethernet support (02ed6bb8) · Commits · 戴 / test

arch/arm/boot/dts/sun8i-v3.dtsi

+13 −0

Original line number	Diff line number	Diff line
		@@ -9,6 +9,19 @@
		compatible = "allwinner,sun8i-v3-ccu";
		};

		&emac {
		/delete-property/ phy-handle;
		/delete-property/ phy-mode;
		};

		&mdio_mux {
		external_mdio: mdio@2 {
		reg = <2>;
		#address-cells = <1>;
		#size-cells = <0>;
		};
		};

		&pio {
		compatible = "allwinner,sun8i-v3-pinctrl";
		};

+52 −0

Original line number	Diff line number	Diff line
		@@ -138,6 +138,15 @@
		};
		};

		syscon: system-control@1c00000 {
		compatible = "allwinner,sun8i-v3s-system-control",
		"allwinner,sun8i-h3-system-control";
		reg = <0x01c00000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		};

		tcon0: lcd-controller@1c0c000 {
		compatible = "allwinner,sun8i-v3s-tcon";
		reg = <0x01c0c000 0x1000>;
		@@ -415,6 +424,49 @@
		#size-cells = <0>;
		};

		emac: ethernet@1c30000 {
		compatible = "allwinner,sun8i-v3s-emac";
		syscon = <&syscon>;
		reg = <0x01c30000 0x10000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq";
		resets = <&ccu RST_BUS_EMAC>;
		reset-names = "stmmaceth";
		clocks = <&ccu CLK_BUS_EMAC>;
		clock-names = "stmmaceth";
		phy-handle = <&int_mii_phy>;
		phy-mode = "mii";
		status = "disabled";

		mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		};

		mdio_mux: mdio-mux {
		compatible = "allwinner,sun8i-h3-mdio-mux";
		#address-cells = <1>;
		#size-cells = <0>;

		mdio-parent-bus = <&mdio>;
		/* Only one MDIO is usable at the time */
		internal_mdio: mdio@1 {
		compatible = "allwinner,sun8i-h3-mdio-internal";
		reg = <1>;
		#address-cells = <1>;
		#size-cells = <0>;

		int_mii_phy: ethernet-phy@1 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <1>;
		clocks = <&ccu CLK_BUS_EPHY>;
		resets = <&ccu RST_BUS_EPHY>;
		};
		};
		};
		};

		spi0: spi@1c68000 {
		compatible = "allwinner,sun8i-h3-spi";
		reg = <0x01c68000 0x1000>;