drm/i915/display: Group DC9 mask set (02d794a3) · Commits · 戴 / test

DC9 has a separate HW flow from the rest of the DC states and it is available in GEN9 LP platforms and on GEN11 and newer, so here moving the assignment of the mask to a single conditional block to simplifly code. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by:

José Roberto de Souza <jose.souza@intel.com> Reviewed-by:

Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201111162408.98002-1-jose.souza@intel.com

drivers/gpu/drm/i915/display/intel_display_power.c

+8 −10

Original line number	Diff line number	Diff line
		@@ -4497,26 +4497,24 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
		max_dc = 3;
		else
		max_dc = 4;
		/*
		* DC9 has a separate HW flow from the rest of the DC states,
		* not depending on the DMC firmware. It's needed by system
		* suspend/resume, so allow it unconditionally.
		*/
		mask = DC_STATE_EN_DC9;
		} else if (IS_GEN(dev_priv, 11)) {
		max_dc = 2;
		mask = DC_STATE_EN_DC9;
		} else if (IS_GEN(dev_priv, 10) \|\| IS_GEN9_BC(dev_priv)) {
		max_dc = 2;
		mask = 0;
		} else if (IS_GEN9_LP(dev_priv)) {
		max_dc = 1;
		mask = DC_STATE_EN_DC9;
		} else {
		max_dc = 0;
		mask = 0;
		}

		/*
		* DC9 has a separate HW flow from the rest of the DC states,
		* not depending on the DMC firmware. It's needed by system
		* suspend/resume, so allow it unconditionally.
		*/
		mask = IS_GEN9_LP(dev_priv) \|\| INTEL_GEN(dev_priv) >= 11 ?
		DC_STATE_EN_DC9 : 0;

		if (!dev_priv->params.disable_power_well)
		max_dc = 0;

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