Commit 02c52f1e authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Disable pipe gamma when C8 pixel format is used 



Planes scanning out C8 will want to use the legacy lut as
their palette. That means the LUT content are unlikely to
be useful for gamma correction on other planes. Thus we
should disable pipe gamma for all the other planes. And
we should reject any non legacy LUT configurations when
C8 planes are present.

Fixes the appearance of the hw cursor when running
X -depth 8.

Note that CHV with it's independent CGM degamma/gamma LUTs
could probably use the CGM for gamma correction even when
the legacy LUT is used for C8. But that would require a
new uapi for configuring the legacy LUT and CGM LUTs at
the same time. Totally not worth it.

v2: Fix typo (Uma)
    Rebase

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-7-ville.syrjala@linux.intel.com
parent 0593d2cd

drivers/gpu/drm/i915/intel_atomic_plane.c

+5 −0
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ 


	new_crtc_state->active_planes &= ~BIT(plane->id);

	new_crtc_state->nv12_planes &= ~BIT(plane->id);

	new_crtc_state->c8_planes &= ~BIT(plane->id);

	new_plane_state->base.visible = false;



	if (!new_plane_state->base.crtc && !old_plane_state->base.crtc)
@@ -136,6 +137,10 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_ 
	    new_plane_state->base.fb->format->format == DRM_FORMAT_NV12)

		new_crtc_state->nv12_planes |= BIT(plane->id);



	if (new_plane_state->base.visible &&

	    new_plane_state->base.fb->format->format == DRM_FORMAT_C8)

		new_crtc_state->c8_planes |= BIT(plane->id);



	if (new_plane_state->base.visible || old_plane_state->base.visible)

		new_crtc_state->update_planes |= BIT(plane->id);

drivers/gpu/drm/i915/intel_color.c

+7 −1
Original line number Diff line number Diff line
@@ -715,7 +715,13 @@ int intel_color_check(struct intel_crtc_state *crtc_state) 
	degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;

	gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;



	crtc_state->gamma_enable = gamma_lut || degamma_lut;

	/* C8 needs the legacy LUT all to itself */

	if (crtc_state->c8_planes &&

	    !crtc_state_is_legacy_gamma(crtc_state))

		return -EINVAL;



	crtc_state->gamma_enable = (gamma_lut || degamma_lut) &&

		!crtc_state->c8_planes;



	if (INTEL_GEN(dev_priv) >= 9 ||

	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -944,6 +944,7 @@ struct intel_crtc_state { 
	/* bitmask of visible planes (enum plane_id) */

	u8 active_planes;

	u8 nv12_planes;

	u8 c8_planes;



	/* bitmask of planes that will be updated during the commit */

	u8 update_planes;

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