Commit 02b4e275 authored by Russell King's avatar Russell King
Browse files

ARM: v7 setup function should invalidate L1 cache 



All ARMv5 and older CPUs invalidate their caches in the early assembly
setup function, prior to enabling the MMU.  This is because the L1
cache should not contain any data relevant to the execution of the
kernel at this point; all data should have been flushed out to memory.

This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed,
these typically do not search their caches when caching is disabled (as
it needs to be when the MMU is disabled) so this change should be safe.

ARMv7 allows there to be CPUs which search their caches while caching is
disabled, and it's permitted that the cache is uninitialised at boot;
for these, the architecture reference manual requires that an
implementation specific code sequence is used immediately after reset
to ensure that the cache is placed into a sane state.  Such
functionality is definitely outside the remit of the Linux kernel, and
must be done by the SoC's firmware before _any_ CPU gets to the Linux
kernel.

Changing the data cache clean+invalidate to a mere invalidate allows us
to get rid of a lot of platform specific hacks around this issue for
their secondary CPU bringup paths - some of which were buggy.

Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Tested-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Tested-by: default avatarHeiko Stuebner <heiko@sntech.de>
Tested-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: default avatarShawn Guo <shawn.guo@linaro.org>
Tested-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Tested-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Tested-by: default avatarMichal Simek <michal.simek@xilinx.com>
Tested-by: default avatarWei Xu <xuwei5@hisilicon.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
parent 6a53bc75

arch/arm/mach-bcm/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -43,5 +43,5 @@ obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o 
ifeq ($(CONFIG_ARCH_BRCMSTB),y)

CFLAGS_platsmp-brcmstb.o	+= -march=armv7-a

obj-y				+= brcmstb.o

obj-$(CONFIG_SMP)		+= headsmp-brcmstb.o platsmp-brcmstb.o

obj-$(CONFIG_SMP)		+= platsmp-brcmstb.o

endif

arch/arm/mach-bcm/brcmstb.h

deleted100644 → 0
+0 −19
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2013-2014 Broadcom Corporation

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation version 2.

 *

 * This program is distributed "as is" WITHOUT ANY WARRANTY of any

 * kind, whether express or implied; without even the implied warranty

 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef __BRCMSTB_H__

#define __BRCMSTB_H__



void brcmstb_secondary_startup(void);



#endif /* __BRCMSTB_H__ */

arch/arm/mach-bcm/headsmp-brcmstb.S

deleted100644 → 0
+0 −33
Original line number Diff line number Diff line 
/*

 * SMP boot code for secondary CPUs

 * Based on arch/arm/mach-tegra/headsmp.S

 *

 * Copyright (C) 2010 NVIDIA, Inc.

 * Copyright (C) 2013-2014 Broadcom Corporation

 *

 * This program is free software; you can redistribute it and/or

 * modify it under the terms of the GNU General Public License as

 * published by the Free Software Foundation version 2.

 *

 * This program is distributed "as is" WITHOUT ANY WARRANTY of any

 * kind, whether express or implied; without even the implied warranty

 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#include <asm/assembler.h>

#include <linux/linkage.h>

#include <linux/init.h>



        .section ".text.head", "ax"



ENTRY(brcmstb_secondary_startup)

        /*

         * Ensure CPU is in a sane state by disabling all IRQs and switching

         * into SVC mode.

         */

        setmode	PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0



        bl      v7_invalidate_l1

        b       secondary_startup

ENDPROC(brcmstb_secondary_startup)

arch/arm/mach-bcm/platsmp-brcmstb.c

+1 −3
Original line number Diff line number Diff line
@@ -30,8 +30,6 @@ 
#include <asm/mach-types.h>

#include <asm/smp_plat.h>



#include "brcmstb.h"



enum {

	ZONE_MAN_CLKEN_MASK		= BIT(0),

	ZONE_MAN_RESET_CNTL_MASK	= BIT(1),
@@ -153,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu) 
	 * Set the reset vector to point to the secondary_startup

	 * routine

	 */

	cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup));

	cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));



	/* Unhalt the cpu */

	cpu_rst_cfg_set(cpu, 0);

arch/arm/mach-berlin/headsmp.S

+0 −6
Original line number Diff line number Diff line
@@ -12,12 +12,6 @@ 
#include <linux/init.h>

#include <asm/assembler.h>



ENTRY(berlin_secondary_startup)

 ARM_BE8(setend be)

	bl	v7_invalidate_l1

	b       secondary_startup

ENDPROC(berlin_secondary_startup)



/*

 * If the following instruction is set in the reset exception vector, CPUs

 * will fetch the value of the software reset address vector when being

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