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It seems that in qemu, we can see an interrupt in R3 despite the fact that it's masked in W1. The chip doesn't actually issue an interrupt, but we can "see" it when taking an interrupt for the other channel. This may be a qemu bug ... or not, so let's be safe and avoid calling into the UART layer when that happens which woulc cause a crash. Signed-off-by:Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by:
Rob Landley <rob@landley.net>
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