Commit 02ab1f50 authored by Andrew Scull's avatar Andrew Scull Committed by Will Deacon
Browse files

arm64: Unify WORKAROUND_SPECULATIVE_AT_{NVHE,VHE} 



Errata 1165522, 1319367 and 1530923 each allow TLB entries to be
allocated as a result of a speculative AT instruction. In order to
avoid mandating VHE on certain affected CPUs, apply the workaround to
both the nVHE and the VHE case for all affected CPUs.

Signed-off-by: default avatarAndrew Scull <ascull@google.com>
Acked-by: default avatarWill Deacon <will@kernel.org>
CC: Marc Zyngier <maz@kernel.org>
CC: James Morse <james.morse@arm.com>
CC: Suzuki K Poulose <suzuki.poulose@arm.com>
CC: Will Deacon <will@kernel.org>
CC: Steven Price <steven.price@arm.com>
Link: https://lore.kernel.org/r/20200504094858.108917-1-ascull@google.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 6a8b55ed

arch/arm64/Kconfig

+18 −21
Original line number Diff line number Diff line
@@ -524,13 +524,13 @@ config ARM64_ERRATUM_1418040 


	  If unsure, say Y.



config ARM64_WORKAROUND_SPECULATIVE_AT_VHE

config ARM64_WORKAROUND_SPECULATIVE_AT

	bool



config ARM64_ERRATUM_1165522

	bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	select ARM64_WORKAROUND_SPECULATIVE_AT

	help

	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
@@ -540,10 +540,23 @@ config ARM64_ERRATUM_1165522 


	  If unsure, say Y.



config ARM64_ERRATUM_1319367

	bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT

	help

	  This option adds work arounds for ARM Cortex-A57 erratum 1319537

	  and A72 erratum 1319367



	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by

	  speculating an AT instruction during a guest context switch.



	  If unsure, say Y.



config ARM64_ERRATUM_1530923

	bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	select ARM64_WORKAROUND_SPECULATIVE_AT

	help

	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.
@@ -569,22 +582,6 @@ config ARM64_ERRATUM_1286807 
	  invalidated has been observed by other observers. The

	  workaround repeats the TLBI+DSB operation.



config ARM64_WORKAROUND_SPECULATIVE_AT_NVHE

	bool



config ARM64_ERRATUM_1319367

	bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_NVHE

	help

	  This option adds work arounds for ARM Cortex-A57 erratum 1319537

	  and A72 erratum 1319367



	  Cortex-A57 and A72 cores could end-up with corrupted TLBs by

	  speculating an AT instruction during a guest context switch.



	  If unsure, say Y.



config ARM64_ERRATUM_1463225

	bool "Cortex-A76: Software Step might prevent interrupt recognition"

	default y

arch/arm64/include/asm/cpucaps.h

+7 −8
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ 
#define ARM64_SSBS				34

#define ARM64_WORKAROUND_1418040		35

#define ARM64_HAS_SB				36

#define ARM64_WORKAROUND_SPECULATIVE_AT_VHE	37

#define ARM64_WORKAROUND_SPECULATIVE_AT	37

#define ARM64_HAS_ADDRESS_AUTH_ARCH		38

#define ARM64_HAS_ADDRESS_AUTH_IMP_DEF		39

#define ARM64_HAS_GENERIC_AUTH_ARCH		40
@@ -55,13 +55,12 @@ 
#define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM	45

#define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM	46

#define ARM64_WORKAROUND_1542419		47

#define ARM64_WORKAROUND_SPECULATIVE_AT_NVHE	48

#define ARM64_HAS_E0PD				49

#define ARM64_HAS_RNG				50

#define ARM64_HAS_AMU_EXTN			51

#define ARM64_HAS_ADDRESS_AUTH			52

#define ARM64_HAS_GENERIC_AUTH			53

#define ARM64_HAS_E0PD				48

#define ARM64_HAS_RNG				49

#define ARM64_HAS_AMU_EXTN			50

#define ARM64_HAS_ADDRESS_AUTH			51

#define ARM64_HAS_GENERIC_AUTH			52



#define ARM64_NCAPS				54

#define ARM64_NCAPS				53



#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/kvm_host.h

+0 −4
Original line number Diff line number Diff line
@@ -573,10 +573,6 @@ static inline bool kvm_arch_requires_vhe(void) 
	if (system_supports_sve())

		return true;



	/* Some implementations have defects that confine them to VHE */

	if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE))

		return true;



	return false;

}

arch/arm64/include/asm/kvm_hyp.h

+1 −1
Original line number Diff line number Diff line
@@ -102,7 +102,7 @@ static __always_inline void __hyp_text __load_guest_stage2(struct kvm *kvm) 
	 * above before we can switch to the EL1/EL0 translation regime used by

	 * the guest.

	 */

	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT_VHE));

	asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT));

}



#endif /* __ARM64_KVM_HYP_H__ */

arch/arm64/kernel/cpu_errata.c

+11 −14
Original line number Diff line number Diff line
@@ -635,7 +635,7 @@ has_neoverse_n1_erratum_1542419(const struct arm64_cpu_capabilities *entry, 
	return is_midr_in_range(midr, &range) && has_dic;

}



#if defined(CONFIG_HARDEN_EL2_VECTORS) || defined(CONFIG_ARM64_ERRATUM_1319367)

#if defined(CONFIG_HARDEN_EL2_VECTORS)



static const struct midr_range ca57_a72[] = {

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
@@ -757,12 +757,16 @@ static const struct arm64_cpu_capabilities erratum_843419_list[] = { 
};

#endif



#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_VHE

static const struct midr_range erratum_speculative_at_vhe_list[] = {

#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT

static const struct midr_range erratum_speculative_at_list[] = {

#ifdef CONFIG_ARM64_ERRATUM_1165522

	/* Cortex A76 r0p0 to r2p0 */

	MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 2, 0),

#endif

#ifdef CONFIG_ARM64_ERRATUM_1319367

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),

#endif

#ifdef CONFIG_ARM64_ERRATUM_1530923

	/* Cortex A55 r0p0 to r2p0 */

	MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
@@ -897,11 +901,11 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		ERRATA_MIDR_RANGE_LIST(erratum_1418040_list),

	},

#endif

#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT_VHE

#ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT

	{

		.desc = "ARM errata 1165522, 1530923",

		.capability = ARM64_WORKAROUND_SPECULATIVE_AT_VHE,

		ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_vhe_list),

		.desc = "ARM errata 1165522, 1319367, 1530923",

		.capability = ARM64_WORKAROUND_SPECULATIVE_AT,

		ERRATA_MIDR_RANGE_LIST(erratum_speculative_at_list),

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1463225
@@ -934,13 +938,6 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.matches = has_neoverse_n1_erratum_1542419,

		.cpu_enable = cpu_enable_trap_ctr_access,

	},

#endif

#ifdef CONFIG_ARM64_ERRATUM_1319367

	{

		.desc = "ARM erratum 1319367",

		.capability = ARM64_WORKAROUND_SPECULATIVE_AT_NVHE,

		ERRATA_MIDR_RANGE_LIST(ca57_a72),

	},

#endif

	{

	}

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