Merge tag 'x86_asm_for_v5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (029f56db) · Commits · 戴 / test

arch/x86/boot/compressed/pgtable_64.c

+0 −9

Original line number	Diff line number	Diff line
		@@ -5,15 +5,6 @@
		#include "pgtable.h"
		#include "../string.h"

		/*
		* __force_order is used by special_insns.h asm code to force instruction
		* serialization.
		*
		* It is not referenced from the code, but GCC < 5 with -fPIE would fail
		* due to an undefined symbol. Define it to make these ancient GCCs work.
		*/
		unsigned long __force_order;

		#define BIOS_START_MIN 0x20000U /* 128K, less than this is insane */
		#define BIOS_START_MAX 0x9f000U /* 640K, absolute maximum */

arch/x86/include/asm/special_insns.h

+15 −13

Original line number	Diff line number	Diff line
		@@ -11,45 +11,47 @@
		#include <linux/jump_label.h>

		/*
		* Volatile isn't enough to prevent the compiler from reordering the
		* read/write functions for the control registers and messing everything up.
		* A memory clobber would solve the problem, but would prevent reordering of
		* all loads stores around it, which can hurt performance. Solution is to
		* use a variable and mimic reads and writes to it to enforce serialization
		* The compiler should not reorder volatile asm statements with respect to each
		* other: they should execute in program order. However GCC 4.9.x and 5.x have
		* a bug (which was fixed in 8.1, 7.3 and 6.5) where they might reorder
		* volatile asm. The write functions are not affected since they have memory
		* clobbers preventing reordering. To prevent reads from being reordered with
		* respect to writes, use a dummy memory operand.
		*/
		extern unsigned long __force_order;

		#define __FORCE_ORDER "m"((unsigned int )0x1000UL)

		void native_write_cr0(unsigned long val);

		static inline unsigned long native_read_cr0(void)
		{
		unsigned long val;
		asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
		asm volatile("mov %%cr0,%0\n\t" : "=r" (val) : __FORCE_ORDER);
		return val;
		}

		static __always_inline unsigned long native_read_cr2(void)
		{
		unsigned long val;
		asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
		asm volatile("mov %%cr2,%0\n\t" : "=r" (val) : __FORCE_ORDER);
		return val;
		}

		static __always_inline void native_write_cr2(unsigned long val)
		{
		asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
		asm volatile("mov %0,%%cr2": : "r" (val) : "memory");
		}

		static inline unsigned long __native_read_cr3(void)
		{
		unsigned long val;
		asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
		asm volatile("mov %%cr3,%0\n\t" : "=r" (val) : __FORCE_ORDER);
		return val;
		}

		static inline void native_write_cr3(unsigned long val)
		{
		asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
		asm volatile("mov %0,%%cr3": : "r" (val) : "memory");
		}

		static inline unsigned long native_read_cr4(void)
		@@ -64,10 +66,10 @@ static inline unsigned long native_read_cr4(void)
		asm volatile("1: mov %%cr4, %0\n"
		"2:\n"
		_ASM_EXTABLE(1b, 2b)
		: "=r" (val), "=m" (__force_order) : "0" (0));
		: "=r" (val) : "0" (0), __FORCE_ORDER);
		#else
		/* CR4 always exists on x86_64. */
		asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
		asm volatile("mov %%cr4,%0\n\t" : "=r" (val) : __FORCE_ORDER);
		#endif
		return val;
		}

arch/x86/include/asm/uaccess.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -418,7 +418,7 @@ do { \
		"2:\n" \
		".section .fixup,\"ax\"\n" \
		"3: mov %[efault],%[errout]\n" \
		" xor"itype" %[output],%[output]\n" \
		" xorl %k[output],%k[output]\n" \
		" jmp 2b\n" \
		".previous\n" \
		_ASM_EXTABLE_UA(1b, 3b) \

arch/x86/kernel/cpu/common.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -360,7 +360,7 @@ void native_write_cr0(unsigned long val)
		unsigned long bits_missing = 0;

		set_register:
		asm volatile("mov %0,%%cr0": "+r" (val), "+m" (__force_order));
		asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");

		if (static_branch_likely(&cr_pinning)) {
		if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
		@@ -379,7 +379,7 @@ void native_write_cr4(unsigned long val)
		unsigned long bits_changed = 0;

		set_register:
		asm volatile("mov %0,%%cr4": "+r" (val), "+m" (cr4_pinned_bits));
		asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");

		if (static_branch_likely(&cr_pinning)) {
		if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {

Admin message