Commit 0299a1a8 authored by Jean-Philippe Brucker's avatar Jean-Philippe Brucker Committed by Will Deacon
Browse files

iommu/arm-smmu-v3: Manage ASIDs with xarray 



In preparation for sharing some ASIDs with the CPU, use a global xarray to
store ASIDs and their context. ASID#0 is now reserved, and the ASID
space is global.

Signed-off-by: default avatarJean-Philippe Brucker <jean-philippe@linaro.org>
Link: https://lore.kernel.org/r/20200519175502.2504091-9-jean-philippe@linaro.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 52f3fab0

drivers/iommu/arm-smmu-v3.c

+18 −9
Original line number Diff line number Diff line
@@ -667,7 +667,6 @@ struct arm_smmu_device { 


#define ARM_SMMU_MAX_ASIDS		(1 << 16)

	unsigned int			asid_bits;

	DECLARE_BITMAP(asid_map, ARM_SMMU_MAX_ASIDS);



#define ARM_SMMU_MAX_VMIDS		(1 << 16)

	unsigned int			vmid_bits;
@@ -727,6 +726,8 @@ struct arm_smmu_option_prop { 
	const char *prop;

};



static DEFINE_XARRAY_ALLOC1(asid_xa);



static struct arm_smmu_option_prop arm_smmu_options[] = {

	{ ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },

	{ ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
@@ -1765,6 +1766,14 @@ static void arm_smmu_free_cd_tables(struct arm_smmu_domain *smmu_domain) 
	cdcfg->cdtab = NULL;

}



static void arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd)

{

	if (!cd->asid)

		return;



	xa_erase(&asid_xa, cd->asid);

}



/* Stream table manipulation functions */

static void

arm_smmu_write_strtab_l1_desc(__le64 *dst, struct arm_smmu_strtab_l1_desc *desc)
@@ -2450,10 +2459,9 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) 
	if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {

		struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;



		if (cfg->cdcfg.cdtab) {

		if (cfg->cdcfg.cdtab)

			arm_smmu_free_cd_tables(smmu_domain);

			arm_smmu_bitmap_free(smmu->asid_map, cfg->cd.asid);

		}

		arm_smmu_free_asid(&cfg->cd);

	} else {

		struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg;

		if (cfg->vmid)
@@ -2468,14 +2476,15 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, 
				       struct io_pgtable_cfg *pgtbl_cfg)

{

	int ret;

	int asid;

	u32 asid;

	struct arm_smmu_device *smmu = smmu_domain->smmu;

	struct arm_smmu_s1_cfg *cfg = &smmu_domain->s1_cfg;

	typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = &pgtbl_cfg->arm_lpae_s1_cfg.tcr;



	asid = arm_smmu_bitmap_alloc(smmu->asid_map, smmu->asid_bits);

	if (asid < 0)

		return asid;

	ret = xa_alloc(&asid_xa, &asid, &cfg->cd,

		       XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL);

	if (ret)

		return ret;



	cfg->s1cdmax = master->ssid_bits;
@@ -2508,7 +2517,7 @@ static int arm_smmu_domain_finalise_s1(struct arm_smmu_domain *smmu_domain, 
out_free_cd_tables:

	arm_smmu_free_cd_tables(smmu_domain);

out_free_asid:

	arm_smmu_bitmap_free(smmu->asid_map, asid);

	arm_smmu_free_asid(&cfg->cd);

	return ret;

}

CRA Git | Maintained and supported by SUSTech CRA and CCSE