Commit 0285827d authored by Claudiu Beznea's avatar Claudiu Beznea Committed by Thierry Reding
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pwm: atmel: Add support for controllers with 32 bit counters 



SAM9X60's PWM controller uses 32 bits counters thus it could generate
signals with higher period and duty cycles than the old ones. Prepare
the current driver to be able to work with old controllers (that uses
16 bits counters) and with the new SAM9X60's controller, by providing
counters information based on compatible string.

Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent 53784159

drivers/pwm/pwm-atmel.c

+23 −11
Original line number Diff line number Diff line
@@ -48,15 +48,11 @@ 
#define PWMV2_CPRD		0x0C

#define PWMV2_CPRDUPD		0x10



/*

 * Max value for duty and period

 *

 * Although the duty and period register is 32 bit,

 * however only the LSB 16 bits are significant.

 */

#define PWM_MAX_DTY		0xFFFF

#define PWM_MAX_PRD		0xFFFF

#define PRD_MAX_PRES		10

/* Max values for period and prescaler */



/* Only the LSB 16 bits are significant. */

#define PWM_MAXV1_PRD		0xFFFF

#define PRD_MAXV1_PRES		10



struct atmel_pwm_registers {

	u8 period;
@@ -65,8 +61,14 @@ struct atmel_pwm_registers { 
	u8 duty_upd;

};



struct atmel_pwm_config {

	u32 max_period;

	u32 max_pres;

};



struct atmel_pwm_data {

	struct atmel_pwm_registers regs;

	struct atmel_pwm_config cfg;

};



struct atmel_pwm_chip {
@@ -125,10 +127,10 @@ static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip, 
	cycles *= clk_get_rate(atmel_pwm->clk);

	do_div(cycles, NSEC_PER_SEC);



	for (*pres = 0; cycles > PWM_MAX_PRD; cycles >>= 1)

	for (*pres = 0; cycles > atmel_pwm->data->cfg.max_period; cycles >>= 1)

		(*pres)++;



	if (*pres > PRD_MAX_PRES) {

	if (*pres > atmel_pwm->data->cfg.max_pres) {

		dev_err(chip->dev, "pres exceeds the maximum value\n");

		return -EINVAL;

	}
@@ -288,6 +290,11 @@ static const struct atmel_pwm_data atmel_pwm_data_v1 = { 
		.duty		= PWMV1_CDTY,

		.duty_upd	= PWMV1_CUPD,

	},

	.cfg = {

		/* 16 bits to keep period and duty. */

		.max_period	= PWM_MAXV1_PRD,

		.max_pres	= PRD_MAXV1_PRES,

	},

};



static const struct atmel_pwm_data atmel_pwm_data_v2 = {
@@ -297,6 +304,11 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = { 
		.duty		= PWMV2_CDTY,

		.duty_upd	= PWMV2_CDTYUPD,

	},

	.cfg = {

		/* 16 bits to keep period and duty. */

		.max_period	= PWM_MAXV1_PRD,

		.max_pres	= PRD_MAXV1_PRES,

	},

};



static const struct platform_device_id atmel_pwm_devtypes[] = {

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