Commit 027dfac6 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

powerpc: Various typo fixes 



Signed-off-by: default avatarAndrea Gelmini <andrea.gelmini@gelma.net>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent e289086f

Documentation/devicetree/bindings/rtc/rtc-opal.txt

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Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ IBM OPAL real-time clock 
------------------------



Required properties:

- comapatible: Should be "ibm,opal-rtc"

- compatible: Should be "ibm,opal-rtc"



Optional properties:

- wakeup-source: Decides if the wakeup is supported or not

arch/powerpc/crypto/aes-spe-regs.h

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Original line number Diff line number Diff line
@@ -18,7 +18,7 @@ 
#define rLN r7	/* length of data to be processed			*/

#define rIP r8	/* potiner to IV (CBC/CTR/XTS modes)			*/

#define rKT r9	/* pointer to tweak key (XTS mode)			*/

#define rT0 r11	/* pointers to en-/decrpytion tables			*/

#define rT0 r11	/* pointers to en-/decryption tables			*/

#define rT1 r10

#define rD0 r9	/* data 						*/

#define rD1 r14

arch/powerpc/include/asm/book3s/64/mmu-hash.h

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@@ -434,7 +434,7 @@ extern void slb_set_size(u16 size); 
 * function.  Used in slb_allocate() and do_stab_bolted.  The function

 * computed is: (protovsid*VSID_MULTIPLIER) % VSID_MODULUS

 *

 *	rt = register continaing the proto-VSID and into which the

 *	rt = register containing the proto-VSID and into which the

 *		VSID will be stored

 *	rx = scratch register (clobbered)

 *

arch/powerpc/include/asm/eeh.h

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@@ -57,7 +57,7 @@ struct pci_dn; 
/*

 * The struct is used to trace PE related EEH functionality.

 * In theory, there will have one instance of the struct to

 * be created against particular PE. In nature, PEs corelate

 * be created against particular PE. In nature, PEs correlate

 * to each other. the struct has to reflect that hierarchy in

 * order to easily pick up those affected PEs when one particular

 * PE has EEH errors.

arch/powerpc/include/asm/nohash/32/pte-44x.h

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@@ -32,7 +32,7 @@ 
 *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR

 *

 * Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional

 * TLB2 storage attibute fields. Those are:

 * TLB2 storage attribute fields. Those are:

 *

 *   TLB2:

 *   0...10    11   12   13   14   15   16...31

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