PCI: xilinx: Use of_pci_get_host_bridge_resources() to parse DT (0259882e) · Commits · 戴 / test

drivers/pci/host/pcie-xilinx.c

+5 −102

Original line number	Diff line number	Diff line
		@@ -94,9 +94,6 @@
		/* Number of MSI IRQs */
		#define XILINX_NUM_MSI_IRQS 128

		/* Number of Memory Resources */
		#define XILINX_MAX_NUM_RESOURCES 3

		/**
		* struct xilinx_pcie_port - PCIe port information
		* @reg_base: IO Mapped Register Base
		@@ -105,7 +102,6 @@
		* @root_busno: Root Bus number
		* @dev: Device pointer
		* @irq_domain: IRQ domain pointer
		* @bus_range: Bus range
		* @resources: Bus Resources
		*/
		struct xilinx_pcie_port {
		@@ -658,97 +654,6 @@ static struct pci_bus xilinx_pcie_scan_bus(int nr, struct pci_sys_data sys)
		return bus;
		}

		/**
		* xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
		* @port: PCIe port information
		*
		* Return: '0' on success and error value on failure
		*/
		static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
		{
		struct device *dev = port->dev;
		struct device_node *node = dev->of_node;
		struct resource *mem;
		resource_size_t offset;
		struct of_pci_range_parser parser;
		struct of_pci_range range;
		struct resource_entry *win;
		int err = 0, mem_resno = 0;

		/* Get the ranges */
		if (of_pci_range_parser_init(&parser, node)) {
		dev_err(dev, "missing \"ranges\" property\n");
		return -EINVAL;
		}

		/* Parse the ranges and add the resources found to the list */
		for_each_of_pci_range(&parser, &range) {

		if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
		dev_err(dev, "Maximum memory resources exceeded\n");
		return -EINVAL;
		}

		mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
		if (!mem) {
		err = -ENOMEM;
		goto free_resources;
		}

		of_pci_range_to_resource(&range, node, mem);

		switch (mem->flags & IORESOURCE_TYPE_BITS) {
		case IORESOURCE_MEM:
		offset = range.cpu_addr - range.pci_addr;
		mem_resno++;
		break;
		default:
		err = -EINVAL;
		break;
		}

		if (err < 0) {
		dev_warn(dev, "Invalid resource found %pR\n", mem);
		continue;
		}

		err = request_resource(&iomem_resource, mem);
		if (err)
		goto free_resources;

		pci_add_resource_offset(&port->resources, mem, offset);
		}

		/* Get the bus range */
		if (of_pci_parse_bus_range(node, &port->bus_range)) {
		u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
		u8 last;

		last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
		XILINX_PCIE_BIR_ECAM_SZ_SHIFT;

		port->bus_range = (struct resource) {
		.name = node->name,
		.start = 0,
		.end = last,
		.flags = IORESOURCE_BUS,
		};
		}

		/* Register bus resource */
		pci_add_resource(&port->resources, &port->bus_range);

		return 0;

		free_resources:
		release_child_resources(&iomem_resource);
		resource_list_for_each_entry(win, &port->resources)
		devm_kfree(dev, win->res);
		pci_free_resource_list(&port->resources);

		return err;
		}

		/**
		* xilinx_pcie_parse_dt - Parse Device tree
		* @port: PCIe port information
		@@ -803,6 +708,8 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
		struct hw_pci hw;
		struct device *dev = &pdev->dev;
		int err;
		resource_size_t iobase = 0;
		LIST_HEAD(res);

		if (!dev->of_node)
		return -ENODEV;
		@@ -827,14 +734,10 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
		return err;
		}

		/*
		* Parse PCI ranges, configuration bus range and
		* request their resources
		*/
		INIT_LIST_HEAD(&port->resources);
		err = xilinx_pcie_parse_and_add_res(port);
		err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff, &res,
		&iobase);
		if (err) {
		dev_err(dev, "Failed adding resources\n");
		dev_err(dev, "Getting bridge resources failed\n");
		return err;
		}

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