Commit 025792ca authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'renesas-arm64-dt-for-v4.15' of... 

Merge tag 'renesas-arm64-dt-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Pull "Renesas ARM64 Based SoC DT Updates for v4.15" from Simon Horman:

* r8a7795 (H3)
  - Use r8a7795-cpg-mssr and r8a7795-sysc bindings
    Hardcoded indicies are replaced with symbols now that they are available

  - Drop bogus HDMI node name suffixes
    Laurent Pinchart says: Node names should not use numerical suffixes if
    the nodes can be distinguished by unit-address

  - Update PFC node name to pin-controller
    Shimoda-san says the PFC node name is changed "from e6060000.pfc and
    pfc@e6060000 to e6060000.pin-controller and pin-controller@e6060000
    like other Renesas SoCs."

* r8a7795 (H3) ES1.0
  - Drop extra zero from XHCI unit address
    This corrects a typo were ee0400000 rather than ee040000 was used
    as the unit address.

* r8a7796 (M3-W)
  - Add FDP1 instance
    Laurent Pinchart says: The r8a7796 has a single FDP1 instance.

* r8a7795 (H3) and r8a7796 (M3-W) SoCs
  - Add USB3.0 peripheral device nodes
    Shimoda-san says that this is not enabled on the Salvator-X/XS boards
    for now as:
     + we need a special cable (USB type-A to A cross cable).
     + we can swap the role by renesas_usb3 driver even if we use a normal
	cable and after usb3.0 host is running, but I think it's a special
	use case.

* r8a7795 (H3) and r8a7796 (M3-W) ULCB boards
  - Enable display output
    Laurent Pinchart says: The DU is already wired up to the HDMI encoder,
    all we need to do is enable it.

* r8a77995 (D3) Draak board
  - Enable EthernetAVB and , USB2.0 Host and PHY

  - Add serial console pins.
    This is safe to do now that r8a77995 PFC driver support is present

* r8a77970 (V3M)
  - Add basic support for SoC and EtherAVB, [H]SCIF and SYS-DMAC nodes
    This is a step towards enabling EtherAVB and [H]SCIF with SYS-DMAC
    in the Eagle board support for which is under review

* tag 'renesas-arm64-dt-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits)
  arm64: dts: renesas: r8a7796: add USB3.0 peripheral device node
  arm64: dts: renesas: r8a7795: add USB3.0 peripheral device node
  arm64: dts: renesas: r8a77995: draak: enable EthernetAVB
  arm64: dts: renesas: r8a77995: draak: enable USB2.0 Host (EHCI/OHCI)
  arm64: dts: renesas: r8a77995: draak: enable USB2.0 PHY
  arm64: dts: renesas: r8a77995: add USB2.0 Host (EHCI/OHCI) device node
  arm64: dts: renesas: r8a77995: Add USB2.0 PHY device node
  arm64: dts: draak: Add serial console pins
  arm64: dts: renesas: r8a77970: add EtherAVB support
  arm64: dts: renesas: r8a77970: add [H]SCIF support
  arm64: dts: renesas: r8a77970: add SYS-DMAC support
  arm64: dts: renesas: initial R8A77970 SoC device tree
  arm64: dts: renesas: r8a77995: Add EthernetAVB device node
  arm64: dts: renesas: r8a77995: add GPIO device nodes
  arm64: dts: renesas: r8a77995: Use r8a7795-cpg-mssr binding definitions
  arm64: dts: renesas: r8a77995: Use r8a7795-sysc binding definitions
  arm64: renesas: Add Renesas R8A77970 Kconfig support
  arm64: dts: renesas: r8a7795: Drop bogus HDMI node names suffixes
  arm64: dts: renesas: ulcb: Enable display output
  arm64: dts: renesas: r8a77995: update PFC node name to pin-controller
  ...
parents 400f170d 2affee61

arch/arm64/Kconfig.platforms

+6 −0
Original line number Diff line number Diff line
@@ -184,6 +184,12 @@ config ARCH_R8A7796 
	help

	  This enables support for the Renesas R-Car M3-W SoC.



config ARCH_R8A77970

	bool "Renesas R-Car V3M SoC Platform"

	depends on ARCH_RENESAS

	help

	  This enables support for the Renesas R-Car V3M SoC.



config ARCH_R8A77995

	bool "Renesas R-Car D3 SoC Platform"

	depends on ARCH_RENESAS

arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -11,7 +11,7 @@ 
#include "r8a7795.dtsi"



&soc {

	xhci1: usb@ee0400000 {

	xhci1: usb@ee040000 {

		compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";

		reg = <0 0xee040000 0 0xc00>;

		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+13 −2
Original line number Diff line number Diff line
@@ -1471,6 +1471,17 @@ 
			status = "disabled";

		};



		usb3_peri0: usb@ee020000 {

			compatible = "renesas,r8a7795-usb3-peri",

				     "renesas,rcar-gen3-usb3-peri";

			reg = <0 0xee020000 0 0x400>;

			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 328>;

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

			resets = <&cpg 328>;

			status = "disabled";

		};



		usb_dmac0: dma-controller@e65a0000 {

			compatible = "renesas,r8a7795-usb-dmac",

				     "renesas,usb-dmac";
@@ -2014,7 +2025,7 @@ 
			renesas,fcp = <&fcpf1>;

		};



		hdmi0: hdmi0@fead0000 {

		hdmi0: hdmi@fead0000 {

			compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";

			reg = <0 0xfead0000 0 0x10000>;

			interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
@@ -2039,7 +2050,7 @@ 
			};

		};



		hdmi1: hdmi1@feae0000 {

		hdmi1: hdmi@feae0000 {

			compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";

			reg = <0 0xfeae0000 0 0x10000>;

			interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/renesas/r8a7796.dtsi

+21 −0
Original line number Diff line number Diff line
@@ -1279,6 +1279,17 @@ 
			status = "disabled";

		};



		usb3_peri0: usb@ee020000 {

			compatible = "renesas,r8a7796-usb3-peri",

				     "renesas,rcar-gen3-usb3-peri";

			reg = <0 0xee020000 0 0x400>;

			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 328>;

			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;

			resets = <&cpg 328>;

			status = "disabled";

		};



		ohci0: usb@ee080000 {

			compatible = "generic-ohci";

			reg = <0 0xee080000 0 0x100>;
@@ -1659,6 +1670,16 @@ 
			/* placeholder */

		};



		fdp1@fe940000 {

			compatible = "renesas,fdp1";

			reg = <0 0xfe940000 0 0x2400>;

			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 119>;

			power-domains = <&sysc R8A7796_PD_A3VC>;

			resets = <&cpg 119>;

			renesas,fcp = <&fcpf0>;

		};



		fcpf0: fcp@fe950000 {

			compatible = "renesas,fcpf";

			reg = <0 0xfe950000 0 0x200>;

arch/arm64/boot/dts/renesas/r8a77970.dtsi

0 → 100644
+366 −0
Original line number Diff line number Diff line 
/*

 * Device Tree Source for the r8a77970 SoC

 *

 * Copyright (C) 2016-2017 Renesas Electronics Corp.

 * Copyright (C) 2017 Cogent Embedded, Inc.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */



#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/renesas-cpg-mssr.h>



/ {

	compatible = "renesas,r8a77970";

	#address-cells = <2>;

	#size-cells = <2>;



	psci {

		compatible = "arm,psci-1.0", "arm,psci-0.2";

		method = "smc";

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		a53_0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0>;

			clocks = <&cpg CPG_CORE 0>;

			power-domains = <&sysc 5>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

		};



		L2_CA53: cache-controller {

			compatible = "cache";

			power-domains = <&sysc 21>;

			cache-unified;

			cache-level = <2>;

		};

	};



	extal_clk: extal {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board */

		clock-frequency = <0>;

	};



	extalr_clk: extalr {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		/* This value must be overridden by the board */

		clock-frequency = <0>;

	};



	/* External SCIF clock - to be overridden by boards that provide it */

	scif_clk: scif {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <0>;

	};



	soc {

		compatible = "simple-bus";

		interrupt-parent = <&gic>;



		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		gic: interrupt-controller@f1010000 {

			compatible = "arm,gic-400";

			#interrupt-cells = <3>;

			#address-cells = <0>;

			interrupt-controller;

			reg = <0 0xf1010000 0 0x1000>,

			      <0 0xf1020000 0 0x20000>,

			      <0 0xf1040000 0 0x20000>,

			      <0 0xf1060000 0 0x20000>;

			interrupts = <GIC_PPI 9	(GIC_CPU_MASK_SIMPLE(1) |

				      IRQ_TYPE_LEVEL_HIGH)>;

			clocks = <&cpg CPG_MOD 408>;

			clock-names = "clk";

			power-domains = <&sysc 32>;

			resets = <&cpg 408>;

		};



		timer {

			compatible = "arm,armv8-timer";

			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |

						  IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |

						  IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |

						  IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |

						  IRQ_TYPE_LEVEL_LOW)>;

		};



		cpg: clock-controller@e6150000 {

			compatible = "renesas,r8a77970-cpg-mssr";

			reg = <0 0xe6150000 0 0x1000>;

			clocks = <&extal_clk>, <&extalr_clk>;

			clock-names = "extal", "extalr";

			#clock-cells = <2>;

			#power-domain-cells = <0>;

			#reset-cells = <1>;

		};



		rst: reset-controller@e6160000 {

			compatible = "renesas,r8a77970-rst";

			reg = <0 0xe6160000 0 0x200>;

		};



		sysc: system-controller@e6180000 {

			compatible = "renesas,r8a77970-sysc";

			reg = <0 0xe6180000 0 0x440>;

			#power-domain-cells = <1>;

		};



		prr: chipid@fff00044 {

			compatible = "renesas,prr";

			reg = <0 0xfff00044 0 4>;

		};



		dmac1: dma-controller@e7300000 {

			compatible = "renesas,dmac-r8a77970",

				     "renesas,rcar-dmac";

			reg = <0 0xe7300000 0 0x10000>;

			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "error",

					  "ch0", "ch1", "ch2", "ch3",

					  "ch4", "ch5", "ch6", "ch7";

			clocks = <&cpg CPG_MOD 218>;

			clock-names = "fck";

			power-domains = <&sysc 32>;

			resets = <&cpg 218>;

			#dma-cells = <1>;

			dma-channels = <8>;

		};



		dmac2: dma-controller@e7310000 {

			compatible = "renesas,dmac-r8a77970",

				     "renesas,rcar-dmac";

			reg = <0 0xe7310000 0 0x10000>;

			interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH

				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "error",

					  "ch0", "ch1", "ch2", "ch3",

					  "ch4", "ch5", "ch6", "ch7";

			clocks = <&cpg CPG_MOD 217>;

			clock-names = "fck";

			power-domains = <&sysc 32>;

			resets = <&cpg 217>;

			#dma-cells = <1>;

			dma-channels = <8>;

		};



		hscif0: serial@e6540000 {

			compatible = "renesas,hscif-r8a77970",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe6540000 0 96>;

			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 520>,

				 <&cpg CPG_CORE 9>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x31>, <&dmac1 0x30>,

			       <&dmac2 0x31>, <&dmac2 0x30>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 520>;

			status = "disabled";

		};



		hscif1: serial@e6550000 {

			compatible = "renesas,hscif-r8a77970",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe6550000 0 96>;

			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 519>,

				 <&cpg CPG_CORE 9>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x33>, <&dmac1 0x32>,

			       <&dmac2 0x33>, <&dmac2 0x32>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 519>;

			status = "disabled";

		};



		hscif2: serial@e6560000 {

			compatible = "renesas,hscif-r8a77970",

				     "renesas,rcar-gen3-hscif",

				     "renesas,hscif";

			reg = <0 0xe6560000 0 96>;

			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 518>,

				 <&cpg CPG_CORE 9>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x35>, <&dmac1 0x34>,

			       <&dmac2 0x35>, <&dmac2 0x34>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 518>;

			status = "disabled";

		};



		hscif3: serial@e66a0000 {

			compatible = "renesas,hscif-r8a77970",

				     "renesas,rcar-gen3-hscif", "renesas,hscif";

			reg = <0 0xe66a0000 0 96>;

			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 517>,

				 <&cpg CPG_CORE 9>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x37>, <&dmac1 0x36>,

			       <&dmac2 0x37>, <&dmac2 0x36>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 517>;

			status = "disabled";

		};



		scif0: serial@e6e60000 {

			compatible = "renesas,scif-r8a77970",

				     "renesas,rcar-gen3-scif",

				     "renesas,scif";

			reg = <0 0xe6e60000 0 64>;

			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 207>,

				 <&cpg CPG_CORE 9>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x51>, <&dmac1 0x50>,

			       <&dmac2 0x51>, <&dmac2 0x50>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 207>;

			status = "disabled";

		};



		scif1: serial@e6e68000 {

			compatible = "renesas,scif-r8a77970",

				     "renesas,rcar-gen3-scif",

				     "renesas,scif";

			reg = <0 0xe6e68000 0 64>;

			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 206>,

				 <&cpg CPG_CORE 9>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x53>, <&dmac1 0x52>,

			       <&dmac2 0x53>, <&dmac2 0x52>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 206>;

			status = "disabled";

		};



		scif3: serial@e6c50000 {

			compatible = "renesas,scif-r8a77970",

				     "renesas,rcar-gen3-scif",

				     "renesas,scif";

			reg = <0 0xe6c50000 0 64>;

			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 204>,

				 <&cpg CPG_CORE 9>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x57>, <&dmac1 0x56>,

			       <&dmac2 0x57>, <&dmac2 0x56>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 204>;

			status = "disabled";

		};



		scif4: serial@e6c40000 {

			compatible = "renesas,scif-r8a77970",

				     "renesas,rcar-gen3-scif", "renesas,scif";

			reg = <0 0xe6c40000 0 64>;

			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&cpg CPG_MOD 203>,

				 <&cpg CPG_CORE 9>,

				 <&scif_clk>;

			clock-names = "fck", "brg_int", "scif_clk";

			dmas = <&dmac1 0x59>, <&dmac1 0x58>,

			       <&dmac2 0x59>, <&dmac2 0x58>;

			dma-names = "tx", "rx", "tx", "rx";

			power-domains = <&sysc 32>;

			resets = <&cpg 203>;

			status = "disabled";

		};



		avb: ethernet@e6800000 {

			compatible = "renesas,etheravb-r8a77970",

				     "renesas,etheravb-rcar-gen3";

			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;

			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "ch0", "ch1", "ch2", "ch3",

					  "ch4", "ch5", "ch6", "ch7",

					  "ch8", "ch9", "ch10", "ch11",

					  "ch12", "ch13", "ch14", "ch15",

					  "ch16", "ch17", "ch18", "ch19",

					  "ch20", "ch21", "ch22", "ch23",

					  "ch24";

			clocks = <&cpg CPG_MOD 812>;

			power-domains = <&sysc 32>;

			resets = <&cpg 812>;

			phy-mode = "rgmii-id";

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};

};

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