Commit 024bb961 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6 

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6:
  sparc64: Kill bogus TPC/address truncation during 32-bit faults.
  sparc: fixup for sparseirq changes
  sparc64: Validate kernel generated fault addresses on sparc64.
  sparc64: On non-Niagara, need to touch NMI watchdog in NOHZ mode.
  sparc64: Implement NMI watchdog on capable cpus.
  sparc: Probe PMU type and record in sparc_pmu_type.
  sparc64: Move generic PCR support code to seperate file.
parents 25431e90 9b026058

arch/sparc/include/asm/cpudata_64.h

+1 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 
typedef struct {

	/* Dcache line 1 */

	unsigned int	__softirq_pending; /* must be 1st, see rtrap.S */

	unsigned int	__pad0;

	unsigned int	__nmi_count;

	unsigned long	clock_tick;	/* %tick's per second */

	unsigned long	__pad;

	unsigned int	__pad1;

arch/sparc/include/asm/irq_64.h

+1 −3
Original line number Diff line number Diff line
@@ -66,9 +66,6 @@ extern void virt_irq_free(unsigned int virt_irq); 
extern void __init init_IRQ(void);

extern void fixup_irqs(void);



extern int register_perfctr_intr(void (*handler)(struct pt_regs *));

extern void release_perfctr_intr(void (*handler)(struct pt_regs *));



static inline void set_softint(unsigned long bits)

{

	__asm__ __volatile__("wr	%0, 0x0, %%set_softint"
@@ -98,5 +95,6 @@ void __trigger_all_cpu_backtrace(void); 
extern void *hardirq_stack[NR_CPUS];

extern void *softirq_stack[NR_CPUS];

#define __ARCH_HAS_DO_SOFTIRQ

#define ARCH_HAS_NMI_WATCHDOG



#endif

arch/sparc/include/asm/kdebug_64.h

+2 −0
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ enum die_val { 
	DIE_TRAP,

	DIE_TRAP_TL1,

	DIE_CALL,

	DIE_NMI,

	DIE_NMIWATCHDOG,

};



#endif

arch/sparc/include/asm/nmi.h

0 → 100644
+10 −0
Original line number Diff line number Diff line 
#ifndef __NMI_H

#define __NMI_H



extern int __init nmi_init(void);

extern void perfctr_irq(int irq, struct pt_regs *regs);

extern void nmi_adjust_hz(unsigned int new_hz);



extern int nmi_usable;



#endif /* __NMI_H */

arch/sparc/include/asm/pcr.h

0 → 100644
+46 −0
Original line number Diff line number Diff line 
#ifndef __PCR_H

#define __PCR_H



struct pcr_ops {

	u64 (*read)(void);

	void (*write)(u64);

};

extern const struct pcr_ops *pcr_ops;



extern void deferred_pcr_work_irq(int irq, struct pt_regs *regs);

extern void schedule_deferred_pcr_work(void);



#define PCR_PIC_PRIV		0x00000001 /* PIC access is privileged */

#define PCR_STRACE		0x00000002 /* Trace supervisor events  */

#define PCR_UTRACE		0x00000004 /* Trace user events        */

#define PCR_N2_HTRACE		0x00000008 /* Trace hypervisor events  */

#define PCR_N2_TOE_OV0		0x00000010 /* Trap if PIC 0 overflows  */

#define PCR_N2_TOE_OV1		0x00000020 /* Trap if PIC 1 overflows  */

#define PCR_N2_MASK0		0x00003fc0

#define PCR_N2_MASK0_SHIFT	6

#define PCR_N2_SL0		0x0003c000

#define PCR_N2_SL0_SHIFT	14

#define PCR_N2_OV0		0x00040000

#define PCR_N2_MASK1		0x07f80000

#define PCR_N2_MASK1_SHIFT	19

#define PCR_N2_SL1		0x78000000

#define PCR_N2_SL1_SHIFT	27

#define PCR_N2_OV1		0x80000000



extern unsigned int picl_shift;



/* In order to commonize as much of the implementation as

 * possible, we use PICH as our counter.  Mostly this is

 * to accomodate Niagara-1 which can only count insn cycles

 * in PICH.

 */

static inline u64 picl_value(unsigned int nmi_hz)

{

	u32 delta = local_cpu_data().clock_tick / (nmi_hz << picl_shift);



	return ((u64)((0 - delta) & 0xffffffff)) << 32;

}



extern u64 pcr_enable;



#endif /* __PCR_H */

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