Commit 0240f307 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'imx-soc-4.17' of... 

Merge tag 'imx-soc-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

Pull "i.MX SoC changes for 4.17" from Shawn Guo:

 - Add i.MX 6SoloLiteLite (i.MX6SLL) SoC support on top of the existing
   i.MX6SL platform code.
 - Improve the SoC revision mapping by utilizing the MAJOR field of
   ANATOP DIGPROG register.
 - Add CPUIDLE_FLAG_TIMER_STOP flag for cpuidle ARM power off state,
   so that we can use ARM generic timer for some i.MX6 SoC.
 - Set low-power interrupt mask for i.MX25 to support STOP mode.
 - Drop EPIT driver as there is no user of it.
 - Simplify the error path of imx6_pm_get_base() a bit.

* tag 'imx-soc-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: imx: Add basic msl support for imx6sll
  ARM: imx: pm-imx6: Return the error directly
  ARM: imx: avic: set low-power interrupt mask for imx25
  ARM: imx: Improve the soc revision calculation flow
  ARM: imx: add timer stop flag to ARM power off state
  ARM: imx: Remove epit support
parents 8694360b dee5dee2

arch/arm/mach-imx/Kconfig

+7 −13
Original line number Diff line number Diff line
@@ -32,18 +32,6 @@ config MXC_DEBUG_BOARD 
	  data/address de-multiplexing and decode, signal level shift,

	  interrupt control and various board functions.



config HAVE_EPIT

	bool



config MXC_USE_EPIT

	bool "Use EPIT instead of GPT"

	depends on HAVE_EPIT

	help

	  Use EPIT as the system timer on systems that have it. Normally you

	  don't have a reason to do so as the EPIT has the same features and

	  uses the same clocks as the GPT. Anyway, on some systems the GPT

	  may be in use for other purposes.



config HAVE_IMX_ANATOP

	bool
@@ -85,7 +73,6 @@ config SOC_IMX31 
config SOC_IMX35

	bool

	select ARCH_MXC_IOMUX_V3

	select HAVE_EPIT

	select MXC_AVIC

	select PINCTRL_IMX35
@@ -512,6 +499,13 @@ config SOC_IMX6SL 
	help

	  This enables support for Freescale i.MX6 SoloLite processor.



config SOC_IMX6SLL

	bool "i.MX6 SoloLiteLite support"

	select SOC_IMX6



	help

	  This enables support for Freescale i.MX6 SoloLiteLite processor.



config SOC_IMX6SX

	bool "i.MX6 SoloX support"

	select PINCTRL_IMX6SX

arch/arm/mach-imx/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -20,7 +20,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 
obj-$(CONFIG_MXC_TZIC) += tzic.o

obj-$(CONFIG_MXC_AVIC) += avic.o



obj-$(CONFIG_MXC_USE_EPIT) += epit.o

obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o



ifeq ($(CONFIG_CPU_IDLE),y)
@@ -78,6 +77,7 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 
endif

obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o

obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o

obj-$(CONFIG_SOC_IMX6SLL) += mach-imx6sl.o

obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o

obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o

obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o

arch/arm/mach-imx/anatop.c

+19 −37
Original line number Diff line number Diff line 
/*

 * Copyright (C) 2013-2015 Freescale Semiconductor, Inc.

 * Copyright 2017-2018 NXP.

 *

 * The code contained herein is licensed under the GNU General Public

 * License. You may obtain a copy of the GNU General Public License
@@ -116,6 +117,7 @@ void __init imx_init_revision_from_anatop(void) 
	unsigned int revision;

	u32 digprog;

	u16 offset = ANADIG_DIGPROG;

	u8 major_part, minor_part;



	np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");

	anatop_base = of_iomap(np, 0);
@@ -127,45 +129,25 @@ void __init imx_init_revision_from_anatop(void) 
	digprog = readl_relaxed(anatop_base + offset);

	iounmap(anatop_base);



	switch (digprog & 0xff) {

	case 0:

	/*

		 * For i.MX6QP, most of the code for i.MX6Q can be resued,

		 * so internally, we identify it as i.MX6Q Rev 2.0

	 * On i.MX7D digprog value match linux version format, so

	 * it needn't map again and we can use register value directly.

	 */

		if (digprog >> 8 & 0x01)

			revision = IMX_CHIP_REVISION_2_0;

		else

			revision = IMX_CHIP_REVISION_1_0;

		break;

	case 1:

		revision = IMX_CHIP_REVISION_1_1;

		break;

	case 2:

		revision = IMX_CHIP_REVISION_1_2;

		break;

	case 3:

		revision = IMX_CHIP_REVISION_1_3;

		break;

	case 4:

		revision = IMX_CHIP_REVISION_1_4;

		break;

	case 5:

		/*

		 * i.MX6DQ TO1.5 is defined as Rev 1.3 in Data Sheet, marked

		 * as 'D' in Part Number last character.

		 */

		revision = IMX_CHIP_REVISION_1_5;

		break;

	default:

	if (of_device_is_compatible(np, "fsl,imx7d-anatop")) {

		revision = digprog & 0xff;

	} else {

		/*

		 * Fail back to return raw register value instead of 0xff.

		 * It will be easy to know version information in SOC if it

		 * can't be recognized by known version. And some chip's (i.MX7D)

		 * digprog value match linux version format, so it needn't map

		 * again and we can use register value directly.

		 * MAJOR: [15:8], the major silicon revison;

		 * MINOR: [7: 0], the minor silicon revison;

		 *

		 * please refer to the i.MX RM for the detailed

		 * silicon revison bit define.

		 * format the major part and minor part to match the

		 * linux kernel soc version format.

		 */

		revision = digprog & 0xff;

		major_part = (digprog >> 8) & 0xf;

		minor_part = digprog & 0xf;

		revision = ((major_part + 1) << 4) | minor_part;

	}



	mxc_set_cpu_type(digprog >> 16 & 0xff);

arch/arm/mach-imx/avic.c

+37 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#include <linux/irqdomain.h>

#include <linux/io.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <asm/mach/irq.h>

#include <asm/exception.h>
@@ -51,7 +52,12 @@ 


#define AVIC_NUM_IRQS 64



/* low power interrupt mask registers */

#define MX25_CCM_LPIMR0	0x68

#define MX25_CCM_LPIMR1	0x6C



static void __iomem *avic_base;

static void __iomem *mx25_ccm_base;

static struct irq_domain *domain;



#ifdef CONFIG_FIQ
@@ -93,6 +99,18 @@ static void avic_irq_suspend(struct irq_data *d) 


	avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask);

	imx_writel(gc->wake_active, avic_base + ct->regs.mask);



	if (mx25_ccm_base) {

		u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?

			MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;

		/*

		 * The interrupts which are still enabled will be used as wakeup

		 * sources. Allow those interrupts in low-power mode.

		 * The LPIMR registers use 0 to allow an interrupt, the AVIC

		 * registers use 1.

		 */

		imx_writel(~gc->wake_active, mx25_ccm_base + offs);

	}

}



static void avic_irq_resume(struct irq_data *d)
@@ -102,6 +120,13 @@ static void avic_irq_resume(struct irq_data *d) 
	int idx = d->hwirq >> 5;



	imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);



	if (mx25_ccm_base) {

		u8 offs = d->hwirq < AVIC_NUM_IRQS / 2 ?

			MX25_CCM_LPIMR0 : MX25_CCM_LPIMR1;



		imx_writel(0xffffffff, mx25_ccm_base + offs);

	}

}



#else
@@ -158,6 +183,18 @@ void __init mxc_init_irq(void __iomem *irqbase) 


	avic_base = irqbase;



	np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");

	mx25_ccm_base = of_iomap(np, 0);



	if (mx25_ccm_base) {

		/*

		 * By default, we mask all interrupts. We set the actual mask

		 * before we go into low-power mode.

		 */

		imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0);

		imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1);

	}



	/* put the AVIC into the reset value with

	 * all interrupts disabled

	 */

arch/arm/mach-imx/cpu.c

+3 −0
Original line number Diff line number Diff line
@@ -135,6 +135,9 @@ struct device * __init imx_soc_device_init(void) 
	case MXC_CPU_IMX6ULL:

		soc_id = "i.MX6ULL";

		break;

	case MXC_CPU_IMX6SLL:

		soc_id = "i.MX6SLL";

		break;

	case MXC_CPU_IMX7D:

		soc_id = "i.MX7D";

		break;

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