Commit 0238d3c7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Will Deacon:
 "The changes are a real mixed bag this time around.

  The only scary looking one from the diffstat is the uapi change to
  asm-generic/mman-common.h, but this has been acked by Arnd and is
  actually just adding a pair of comments in an attempt to prevent
  allocation of some PROT values which tend to get used for
  arch-specific purposes. We'll be using them for Branch Target
  Identification (a CFI-like hardening feature), which is currently
  under review on the mailing list.

  New architecture features:

   - Support for Armv8.5 E0PD, which benefits KASLR in the same way as
     KPTI but without the overhead. This allows KPTI to be disabled on
     CPUs that are not affected by Meltdown, even is KASLR is enabled.

   - Initial support for the Armv8.5 RNG instructions, which claim to
     provide access to a high bandwidth, cryptographically secure
     hardware random number generator. As well as exposing these to
     userspace, we also use them as part of the KASLR seed and to seed
     the crng once all CPUs have come online.

   - Advertise a bunch of new instructions to userspace, including
     support for Data Gathering Hint, Matrix Multiply and 16-bit
     floating point.

  Kexec:

   - Cleanups in preparation for relocating with the MMU enabled

   - Support for loading crash dump kernels with kexec_file_load()

  Perf and PMU drivers:

   - Cleanups and non-critical fixes for a couple of system PMU drivers

  FPU-less (aka broken) CPU support:

   - Considerable fixes to support CPUs without the FP/SIMD extensions,
     including their presence in heterogeneous systems. Good luck
     finding a 64-bit userspace that handles this.

  Modern assembly function annotations:

   - Start migrating our use of ENTRY() and ENDPROC() over to the
     new-fangled SYM_{CODE,FUNC}_{START,END} macros, which are intended
     to aid debuggers

  Kbuild:

   - Cleanup detection of LSE support in the assembler by introducing
     'as-instr'

   - Remove compressed Image files when building clean targets

  IP checksumming:

   - Implement optimised IPv4 checksumming routine when hardware offload
     is not in use. An IPv6 version is in the works, pending testing.

  Hardware errata:

   - Work around Cortex-A55 erratum #1530923

  Shadow call stack:

   - Work around some issues with Clang's integrated assembler not
     liking our perfectly reasonable assembly code

   - Avoid allocating the X18 register, so that it can be used to hold
     the shadow call stack pointer in future

  ACPI:

   - Fix ID count checking in IORT code. This may regress broken
     firmware that happened to work with the old implementation, in
     which case we'll have to revert it and try something else

   - Fix DAIF corruption on return from GHES handler with pseudo-NMIs

  Miscellaneous:

   - Whitelist some CPUs that are unaffected by Spectre-v2

   - Reduce frequency of ASID rollover when KPTI is compiled in but
     inactive

   - Reserve a couple of arch-specific PROT flags that are already used
     by Sparc and PowerPC and are planned for later use with BTI on
     arm64

   - Preparatory cleanup of our entry assembly code in preparation for
     moving more of it into C later on

   - Refactoring and cleanup"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (73 commits)
  arm64: acpi: fix DAIF manipulation with pNMI
  arm64: kconfig: Fix alignment of E0PD help text
  arm64: Use v8.5-RNG entropy for KASLR seed
  arm64: Implement archrandom.h for ARMv8.5-RNG
  arm64: kbuild: remove compressed images on 'make ARCH=arm64 (dist)clean'
  arm64: entry: Avoid empty alternatives entries
  arm64: Kconfig: select HAVE_FUTEX_CMPXCHG
  arm64: csum: Fix pathological zero-length calls
  arm64: entry: cleanup sp_el0 manipulation
  arm64: entry: cleanup el0 svc handler naming
  arm64: entry: mark all entry code as notrace
  arm64: assembler: remove smp_dmb macro
  arm64: assembler: remove inherit_daif macro
  ACPI/IORT: Fix 'Number of IDs' handling in iort_id_map()
  mm: Reserve asm-generic prot flags 0x10 and 0x20 for arch use
  arm64: Use macros instead of hard-coded constants for MAIR_EL1
  arm64: Add KRYO{3,4}XX CPU cores to spectre-v2 safe list
  arm64: kernel: avoid x18 in __cpu_soft_restart
  arm64: kvm: stop treating register x18 as caller save
  arm64/lib: copy_page: avoid x18 register in assembler code
  ...
parents d5226fa6 e533dbe9

Documentation/arm64/cpu-feature-registers.rst

+16 −0
Original line number Diff line number Diff line
@@ -117,6 +117,8 @@ infrastructure: 
     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | RNDR                         | [63-60] |    y    |

     +------------------------------+---------+---------+

     | TS                           | [55-52] |    y    |

     +------------------------------+---------+---------+

     | FHM                          | [51-48] |    y    |
@@ -200,6 +202,12 @@ infrastructure: 
     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | I8MM                         | [55-52] |    y    |

     +------------------------------+---------+---------+

     | DGH                          | [51-48] |    y    |

     +------------------------------+---------+---------+

     | BF16                         | [47-44] |    y    |

     +------------------------------+---------+---------+

     | SB                           | [39-36] |    y    |

     +------------------------------+---------+---------+

     | FRINTTS                      | [35-32] |    y    |
@@ -234,10 +242,18 @@ infrastructure: 
     +------------------------------+---------+---------+

     | Name                         |  bits   | visible |

     +------------------------------+---------+---------+

     | F64MM                        | [59-56] |    y    |

     +------------------------------+---------+---------+

     | F32MM                        | [55-52] |    y    |

     +------------------------------+---------+---------+

     | I8MM                         | [47-44] |    y    |

     +------------------------------+---------+---------+

     | SM4                          | [43-40] |    y    |

     +------------------------------+---------+---------+

     | SHA3                         | [35-32] |    y    |

     +------------------------------+---------+---------+

     | BF16                         | [23-20] |    y    |

     +------------------------------+---------+---------+

     | BitPerm                      | [19-16] |    y    |

     +------------------------------+---------+---------+

     | AES                          | [7-4]   |    y    |

Documentation/arm64/elf_hwcaps.rst

+31 −0
Original line number Diff line number Diff line
@@ -204,6 +204,37 @@ HWCAP2_FRINT 


    Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.



HWCAP2_SVEI8MM



    Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.



HWCAP2_SVEF32MM



    Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.



HWCAP2_SVEF64MM



    Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.



HWCAP2_SVEBF16



    Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.



HWCAP2_I8MM



    Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.



HWCAP2_BF16



    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001.



HWCAP2_DGH



    Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001.



HWCAP2_RNG



    Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.



4. Unused AT_HWCAP bits

-----------------------

Documentation/arm64/silicon-errata.rst

+2 −0
Original line number Diff line number Diff line
@@ -88,6 +88,8 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A76      | #1463225        | ARM64_ERRATUM_1463225       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A55      | #1530923        | ARM64_ERRATUM_1530923       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

arch/arm64/Kconfig

+55 −1
Original line number Diff line number Diff line
@@ -162,6 +162,7 @@ config ARM64 
	select HAVE_PERF_USER_STACK_DUMP

	select HAVE_REGS_AND_STACK_ACCESS_API

	select HAVE_FUNCTION_ARG_ACCESS_API

	select HAVE_FUTEX_CMPXCHG if FUTEX

	select HAVE_RCU_TABLE_FREE

	select HAVE_RSEQ

	select HAVE_STACKPROTECTOR
@@ -302,6 +303,9 @@ config ARCH_SUPPORTS_UPROBES 
config ARCH_PROC_KCORE_TEXT

	def_bool y



config BROKEN_GAS_INST

	def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)



config KASAN_SHADOW_OFFSET

	hex

	depends on KASAN
@@ -515,9 +519,13 @@ config ARM64_ERRATUM_1418040 


	  If unsure, say Y.



config ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	bool



config ARM64_ERRATUM_1165522

	bool "Cortex-A76: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	help

	  This option adds a workaround for ARM Cortex-A76 erratum 1165522.
@@ -527,6 +535,19 @@ config ARM64_ERRATUM_1165522 


	  If unsure, say Y.



config ARM64_ERRATUM_1530923

	bool "Cortex-A55: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_VHE

	help

	  This option adds a workaround for ARM Cortex-A55 erratum 1530923.



	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with

	  corrupted TLBs by speculating an AT instruction during a guest

	  context switch.



	  If unsure, say Y.



config ARM64_ERRATUM_1286807

	bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-after-read ordering violation"

	default y
@@ -543,9 +564,13 @@ config ARM64_ERRATUM_1286807 
	  invalidated has been observed by other observers. The

	  workaround repeats the TLBI+DSB operation.



config ARM64_WORKAROUND_SPECULATIVE_AT_NVHE

	bool



config ARM64_ERRATUM_1319367

	bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"

	default y

	select ARM64_WORKAROUND_SPECULATIVE_AT_NVHE

	help

	  This option adds work arounds for ARM Cortex-A57 erratum 1319537

	  and A72 erratum 1319367
@@ -1364,6 +1389,11 @@ config ARM64_PAN 
	 instruction if the cpu does not implement the feature.



config ARM64_LSE_ATOMICS

	bool

	default ARM64_USE_LSE_ATOMICS

	depends on $(as-instr,.arch_extension lse)



config ARM64_USE_LSE_ATOMICS

	bool "Atomic instructions"

	depends on JUMP_LABEL

	default y
@@ -1485,6 +1515,30 @@ config ARM64_PTR_AUTH 


endmenu



menu "ARMv8.5 architectural features"



config ARM64_E0PD

	bool "Enable support for E0PD"

	default y

	help

	  E0PD (part of the ARMv8.5 extensions) allows us to ensure

	  that EL0 accesses made via TTBR1 always fault in constant time,

	  providing similar benefits to KASLR as those provided by KPTI, but

	  with lower overhead and without disrupting legitimate access to

	  kernel memory such as SPE.



	  This option enables E0PD for TTBR1 where available.



config ARCH_RANDOM

	bool "Enable support for random number generation"

	default y

	help

	  Random number generation (part of the ARMv8.5 Extensions)

	  provides a high bandwidth, cryptographically secure

	  hardware random number generator.



endmenu



config ARM64_SVE

	bool "ARM Scalable Vector Extension support"

	default y
@@ -1545,7 +1599,7 @@ config ARM64_MODULE_PLTS 


config ARM64_PSEUDO_NMI

	bool "Support for NMI-like interrupts"

	select CONFIG_ARM_GIC_V3

	select ARM_GIC_V3

	help

	  Adds support for mimicking Non-Maskable Interrupts through the use of

	  GIC interrupt priority. This support requires version 3 or later of

arch/arm64/Makefile

+5 −12
Original line number Diff line number Diff line
@@ -30,11 +30,8 @@ LDFLAGS_vmlinux += --fix-cortex-a53-843419 
  endif

endif



# Check for binutils support for specific extensions

lseinstr := $(call as-instr,.arch_extension lse,-DCONFIG_AS_LSE=1)



ifeq ($(CONFIG_ARM64_LSE_ATOMICS), y)

  ifeq ($(lseinstr),)

ifeq ($(CONFIG_ARM64_USE_LSE_ATOMICS), y)

  ifneq ($(CONFIG_ARM64_LSE_ATOMICS), y)

$(warning LSE atomics not supported by binutils)

  endif

endif
@@ -45,19 +42,15 @@ cc_has_k_constraint := $(call try-run,echo \ 
		return 0;						\

	}' | $(CC) -S -x c -o "$$TMP" -,,-DCONFIG_CC_HAS_K_CONSTRAINT=1)



ifeq ($(CONFIG_ARM64), y)

brokengasinst := $(call as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n,,-DCONFIG_BROKEN_GAS_INST=1)



  ifneq ($(brokengasinst),)

ifeq ($(CONFIG_BROKEN_GAS_INST),y)

$(warning Detected assembler with broken .inst; disassembly will be unreliable)

endif

endif



KBUILD_CFLAGS	+= -mgeneral-regs-only $(lseinstr) $(brokengasinst)	\

KBUILD_CFLAGS	+= -mgeneral-regs-only	\

		   $(compat_vdso) $(cc_has_k_constraint)

KBUILD_CFLAGS	+= -fno-asynchronous-unwind-tables

KBUILD_CFLAGS	+= $(call cc-disable-warning, psabi)

KBUILD_AFLAGS	+= $(lseinstr) $(brokengasinst) $(compat_vdso)

KBUILD_AFLAGS	+= $(compat_vdso)



KBUILD_CFLAGS	+= $(call cc-option,-mabi=lp64)

KBUILD_AFLAGS	+= $(call cc-option,-mabi=lp64)

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