bpf, riscv: Enable missing verifier_zext optimizations on RV64 (0224b2ac) · Commits · 戴 / test

Commit ("riscv: bpf: eliminate zero extension code-gen") added support for the verifier zero-extension optimization on RV64 and commit ("bpf, riscv: Enable zext optimization for more RV64G ALU ops") enabled it for more instruction cases. However, BPF_LSH BPF_X and BPF_{LSH,RSH,ARSH} BPF_K are still missing the optimization. This patch enables the zero-extension optimization for these remaining cases. Co-developed-by:

Xi Wang <xi.wang@gmail.com> Signed-off-by:

Luke Nelson <luke.r.nels@gmail.com> Signed-off-by:

Daniel Borkmann <daniel@iogearbox.net> Reviewed-by:

Björn Töpel <bjorn.topel@gmail.com> Acked-by:

Björn Töpel <bjorn.topel@gmail.com> Link: https://lore.kernel.org/bpf/20200506000320.28965-2-luke.r.nels@gmail.com

arch/riscv/net/bpf_jit_comp64.c

+4 −4

Original line number	Diff line number	Diff line
		@@ -515,7 +515,7 @@ int bpf_jit_emit_insn(const struct bpf_insn insn, struct rv_jit_context ctx,
		case BPF_ALU \| BPF_LSH \| BPF_X:
		case BPF_ALU64 \| BPF_LSH \| BPF_X:
		emit(is64 ? rv_sll(rd, rd, rs) : rv_sllw(rd, rd, rs), ctx);
		if (!is64)
		if (!is64 && !aux->verifier_zext)
		emit_zext_32(rd, ctx);
		break;
		case BPF_ALU \| BPF_RSH \| BPF_X:
		@@ -692,19 +692,19 @@ out_be:
		case BPF_ALU \| BPF_LSH \| BPF_K:
		case BPF_ALU64 \| BPF_LSH \| BPF_K:
		emit(is64 ? rv_slli(rd, rd, imm) : rv_slliw(rd, rd, imm), ctx);
		if (!is64)
		if (!is64 && !aux->verifier_zext)
		emit_zext_32(rd, ctx);
		break;
		case BPF_ALU \| BPF_RSH \| BPF_K:
		case BPF_ALU64 \| BPF_RSH \| BPF_K:
		emit(is64 ? rv_srli(rd, rd, imm) : rv_srliw(rd, rd, imm), ctx);
		if (!is64)
		if (!is64 && !aux->verifier_zext)
		emit_zext_32(rd, ctx);
		break;
		case BPF_ALU \| BPF_ARSH \| BPF_K:
		case BPF_ALU64 \| BPF_ARSH \| BPF_K:
		emit(is64 ? rv_srai(rd, rd, imm) : rv_sraiw(rd, rd, imm), ctx);
		if (!is64)
		if (!is64 && !aux->verifier_zext)
		emit_zext_32(rd, ctx);
		break;

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