Commit 0220dcd1 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.1' of... 

Merge tag 'phy-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy

 into usb-next

Kishon writes:

phy: for 5.1

  *) Add a new driver to support Armada 3700 COMPHY IP (supports SATA, USB3,
     PCIe)
  *) Add a new driver to support Armada UTMI PHY
  *) Add a new driver to support Cadence D-PHY
  *) Extend omap-usb2 PHY driver to be used for AM654 USB2 PHY
  *) Extend qcom-qmp PHY driver to be used for UFS PHY and USB3 PHY in Qualcomm
     MSM8998
  *) Extend qcom-qusb2 PHY driver to support QUSB2 PHY in Qualcomm MSM8998
  *) Remove module specific code that is present for drivers that can be only
     built-in
  *) Allow Freescale IMX8MQ USB to be used for multiple SoCs and not just
     i.MX8MQ
  *) Cleanups such as switch to SPDX identifier, use readl_poll_timeout macro,
     remove unused headers etc.,

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (32 commits)
  phy: qcom-qmp: Add QMP UFS PHY support for msm8998
  dt-bindings: phy-qcom-qmp: Add qcom,msm8998-qmp-ufs-phy
  phy: bcm-sr-pcie: Change operation when PIPEMUX=1
  phy: Add Cadence D-PHY support
  dt-bindings: phy: Move the Cadence D-PHY bindings
  phy: dphy: Clarify lanes parameter documentation
  phy: dphy: Change units of wakeup and init parameters
  phy: dphy: Remove unused header
  MAINTAINERS: phy: fill Armada 3700 PHY drivers entry
  dt-bindings: phy: mvebu-utmi: add UTMI PHY bindings
  phy: add A3700 UTMI PHY driver
  MAINTAINERS: phy: add entry for Armada 3700 COMPHY driver
  dt-bindings: phy: mvebu-comphy: extend the file to describe a3700 bindings
  phy: add A3700 COMPHY support
  phy: mvebu-cp110-comphy: fix port check in ->xlate()
  phy: armada375-usb2: switch to SPDX license identifier
  phy: make phy-armada375-usb2 explicitly non-modular
  phy: make phy-mvebu-sata explicitly non-modular
  phy: make phy-core explicitly non-modular
  phy: qcom-qusb2: Add QUSB2 PHY support for msm8998
  ...
parents a8ded8eb 203d9b11

Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt

+0 −21
Original line number Diff line number Diff line
@@ -31,28 +31,7 @@ Required subnodes: 
- one subnode per DSI device connected on the DSI bus. Each DSI device should

  contain a reg property encoding its virtual channel.



Cadence DPHY

============



Cadence DPHY block.



Required properties:

- compatible: should be set to "cdns,dphy".

- reg: physical base address and length of the DPHY registers.

- clocks: DPHY reference clocks.

- clock-names: must contain "psm" and "pll_ref".

- #phy-cells: must be set to 0.





Example:

	dphy0: dphy@fd0e0000{

		compatible = "cdns,dphy";

		reg = <0x0 0xfd0e0000 0x0 0x1000>;

		clocks = <&psm_clk>, <&pll_ref_clk>;

		clock-names = "psm", "pll_ref";

		#phy-cells = <0>;

	};



	dsi0: dsi@fd0c0000 {

		compatible = "cdns,dsi";

		reg = <0x0 0xfd0c0000 0x0 0x1000>;

Documentation/devicetree/bindings/phy/cdns,dphy.txt

0 → 100644
+20 −0
Original line number Diff line number Diff line 
Cadence DPHY

============



Cadence DPHY block.



Required properties:

- compatible: should be set to "cdns,dphy".

- reg: physical base address and length of the DPHY registers.

- clocks: DPHY reference clocks.

- clock-names: must contain "psm" and "pll_ref".

- #phy-cells: must be set to 0.



Example:

	dphy0: dphy@fd0e0000{

		compatible = "cdns,dphy";

		reg = <0x0 0xfd0e0000 0x0 0x1000>;

		clocks = <&psm_clk>, <&pll_ref_clk>;

		clock-names = "psm", "pll_ref";

		#phy-cells = <0>;

	};

Documentation/devicetree/bindings/phy/phy-mvebu-comphy.txt

+53 −12
Original line number Diff line number Diff line 
mvebu comphy driver

-------------------

MVEBU comphy drivers

--------------------



A comphy controller can be found on Marvell Armada 7k/8k on the CP110. It

provides a number of shared PHYs used by various interfaces (network, sata,

usb, PCIe...).

COMPHY controllers can be found on the following Marvell MVEBU SoCs:

* Armada 7k/8k (on the CP110)

* Armada 3700

It provides a number of shared PHYs used by various interfaces (network, SATA,

USB, PCIe...).



Required properties:



- compatible: should be "marvell,comphy-cp110"

- reg: should contain the comphy register location and length.

- marvell,system-controller: should contain a phandle to the

                             system controller node.

- compatible: should be one of:

  * "marvell,comphy-cp110" for Armada 7k/8k

  * "marvell,comphy-a3700" for Armada 3700

- reg: should contain the COMPHY register(s) location(s) and length(s).

  * 1 entry for Armada 7k/8k

  * 4 entries for Armada 3700 along with the corresponding reg-names

    properties, memory areas are:

    * Generic COMPHY registers

    * Lane 1 (PCIe/GbE)

    * Lane 0 (USB3/GbE)

    * Lane 2 (SATA/USB3)

- marvell,system-controller: should contain a phandle to the system

			     controller node (only for Armada 7k/8k)

- #address-cells: should be 1.

- #size-cells: should be 0.
@@ -18,11 +29,11 @@ A sub-node is required for each comphy lane provided by the comphy. 


Required properties (child nodes):



- reg: comphy lane number.

- #phy-cells : from the generic phy bindings, must be 1. Defines the

- reg: COMPHY lane number.

- #phy-cells : from the generic PHY bindings, must be 1. Defines the

               input port to use for a given comphy lane.



Example:

Examples:



	cpm_comphy: phy@120000 {

		compatible = "marvell,comphy-cp110";
@@ -41,3 +52,33 @@ Example: 
			#phy-cells = <1>;

		};

	};



	comphy: phy@18300 {

		compatible = "marvell,comphy-a3700";

		reg = <0x18300 0x300>,

		<0x1F000 0x400>,

		<0x5C000 0x400>,

		<0xe0178 0x8>;

		reg-names = "comphy",

		"lane1_pcie_gbe",

		"lane0_usb3_gbe",

		"lane2_sata_usb3";

		#address-cells = <1>;

		#size-cells = <0>;





		comphy0: phy@0 {

			reg = <0>;

			#phy-cells = <1>;

		};



		comphy1: phy@1 {

			reg = <1>;

			#phy-cells = <1>;

		};



		comphy2: phy@2 {

			reg = <2>;

			#phy-cells = <1>;

		};

	};

Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt

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MVEBU A3700 UTMI PHY

--------------------



USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:

* Armada 3700



On Armada 3700, there are two USB controllers, one is compatible with the USB2

and USB3 specifications and supports OTG. The other one is USB2 compliant and

only supports host mode. Both of these controllers come with a slightly

different UTMI PHY.



Required Properties:



- compatible: Should be one of:

	      * "marvell,a3700-utmi-host-phy" for the PHY connected to

	        the USB2 host-only controller.

	      * "marvell,a3700-utmi-otg-phy" for the PHY connected to

	        the USB3 and USB2 OTG capable controller.

- reg: PHY IP register range.

- marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared

			region covering registers related to both the host

			controller and the PHY.

- #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.





Example:



	usb2_utmi_host_phy: phy@5f000 {

		compatible = "marvell,armada-3700-utmi-host-phy";

		reg = <0x5f000 0x800>;

		marvell,usb-misc-reg = <&usb2_syscon>;

		#phy-cells = <0>;

	};



	usb2_syscon: system-controller@5f800 {

		compatible = "marvell,armada-3700-usb2-host-misc", "syscon";

		reg = <0x5f800 0x800>;

	};

Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt

+2 −0
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@ Optional properties: 
		 register files". When set driver will request its

		 phandle as one companion-grf for some special SoCs

		 (e.g RV1108).

 - extcon : phandle to the extcon device providing the cable state for

		 the otg phy.



Required nodes : a sub-node is required for each port the phy provides.

		 The sub-node name is used to identify host or otg port,

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