Commit 0212a048 authored Aug 07, 2020 by Marek Szyprowski Committed by Sylwester Nawrocki Sep 15, 2020

clk: samsung: Keep top BPLL mux on Exynos542x enabled



BPLL clock must not be disabled because it is needed for proper DRAM
operation. This is normally handled by respective memory devfreq driver,
but when that driver is not yet probed or its probe has been deferred
the clock might get disabled what causes board hang. Fix this by calling
clk_prepare_enable() directly from the clock provider driver.

Cc: stable@vger.kernel.org
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Lukasz Luba <lukasz.luba@arm.com>
Tested-by: Lukasz Luba <lukasz.luba@arm.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20200807133143.22748-1-m.szyprowski@samsung.com


Fixes: 6e7674c3 ("memory: Add DMC driver for Exynos5422")
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

parent 9123e3a7

drivers/clk/samsung/clk-exynos5420.c

+5 −0

Original line number	Diff line number	Diff line
		@@ -1655,6 +1655,11 @@ static void __init exynos5x_clk_init(struct device_node *np,
		* main G3D clock enablement status.
		*/
		clk_prepare_enable(__clk_lookup("mout_sw_aclk_g3d"));
		/*
		* Keep top BPLL mux enabled permanently to ensure that DRAM operates
		* properly.
		*/
		clk_prepare_enable(__clk_lookup("mout_bpll"));

		samsung_clk_of_add_provider(np, ctx);
		}

Admin message