Unverified Commit 01ddbbb0 authored by Serge Semin's avatar Serge Semin Committed by Mark Brown
Browse files

spi: dw-dma: Set DMA Level registers on init 



Indeed the registers content doesn't get cleared when the SPI controller
is disabled and enabled. Max burst lengths aren't changed since the Rx and
Tx DMA channels are requested on init stage and are kept acquired until
the device is removed. Obviously SPI controller FIFO depth can't be
changed. Due to all of that we can safely move the DMA Transmit and
Receive data level registers initialization to the SPI controller DMA init
stage (when the SPI controller is being probed) instead of doing it for
each SPI transfer when dma_setup is called. This shall speed the DMA-based
SPI transfer initialization up a bit, particularly if the APB bus is
relatively slow.

Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20200920112322.24585-2-Sergey.Semin@baikalelectronics.ru


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 0e968365

drivers/spi/spi-dw-dma.c

+13 −15
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ static void dw_spi_dma_maxburst_init(struct dw_spi *dws) 
		max_burst = RX_BURST_LEVEL;



	dws->rxburst = min(max_burst, def_burst);

	dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);



	ret = dma_get_slave_caps(dws->txchan, &caps);

	if (!ret && caps.max_burst)
@@ -56,7 +57,19 @@ static void dw_spi_dma_maxburst_init(struct dw_spi *dws) 
	else

		max_burst = TX_BURST_LEVEL;



	/*

	 * Having a Rx DMA channel serviced with higher priority than a Tx DMA

	 * channel might not be enough to provide a well balanced DMA-based

	 * SPI transfer interface. There might still be moments when the Tx DMA

	 * channel is occasionally handled faster than the Rx DMA channel.

	 * That in its turn will eventually cause the SPI Rx FIFO overflow if

	 * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's

	 * cleared by the Rx DMA channel. In order to fix the problem the Tx

	 * DMA activity is intentionally slowed down by limiting the SPI Tx

	 * FIFO depth with a value twice bigger than the Tx burst length.

	 */

	dws->txburst = min(max_burst, def_burst);

	dw_writel(dws, DW_SPI_DMATDLR, dws->txburst);

}



static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
@@ -372,21 +385,6 @@ static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer) 
{

	u16 imr = 0, dma_ctrl = 0;



	/*

	 * Having a Rx DMA channel serviced with higher priority than a Tx DMA

	 * channel might not be enough to provide a well balanced DMA-based

	 * SPI transfer interface. There might still be moments when the Tx DMA

	 * channel is occasionally handled faster than the Rx DMA channel.

	 * That in its turn will eventually cause the SPI Rx FIFO overflow if

	 * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's

	 * cleared by the Rx DMA channel. In order to fix the problem the Tx

	 * DMA activity is intentionally slowed down by limiting the SPI Tx

	 * FIFO depth with a value twice bigger than the Tx burst length

	 * calculated earlier by the dw_spi_dma_maxburst_init() method.

	 */

	dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);

	dw_writel(dws, DW_SPI_DMATDLR, dws->txburst);



	if (xfer->tx_buf)

		dma_ctrl |= SPI_DMA_TDMAE;

	if (xfer->rx_buf)

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