Commit 01d57485 authored Jun 11, 2019 by Will Deacon

arm64: tlbflush: Ensure start/end of address range are aligned to stride



Since commit 3d65b6bb ("arm64: tlbi: Set MAX_TLBI_OPS to
PTRS_PER_PTE"), we resort to per-ASID invalidation when attempting to
perform more than PTRS_PER_PTE invalidation instructions in a single
call to __flush_tlb_range(). Whilst this is beneficial, the mmu_gather
code does not ensure that the end address of the range is rounded-up
to the stride when freeing intermediate page tables in pXX_free_tlb(),
which defeats our range checking.

Align the bounds passed into __flush_tlb_range().

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Reported-by: Hanjun Guo <guohanjun@huawei.com>
Tested-by: Hanjun Guo <guohanjun@huawei.com>
Reviewed-by: Hanjun Guo <guohanjun@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

parent fa63da2a

arch/arm64/include/asm/tlbflush.h

+3 −0

Original line number	Diff line number	Diff line
		@@ -195,6 +195,9 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
		unsigned long asid = ASID(vma->vm_mm);
		unsigned long addr;

		start = round_down(start, stride);
		end = round_up(end, stride);

		if ((end - start) >= (MAX_TLBI_OPS * stride)) {
		flush_tlb_mm(vma->vm_mm);
		return;

Admin message