Commit 01b09d53 authored by Sean Paul's avatar Sean Paul Committed by Rob Clark
Browse files

drm/msm: Remove dpu_encoder_phys_ops->hw_reset() 



We call out of the virt encoder into phys only to call back into the
virt for hw reset. So remove the indirection and just call the virt
function directly.

Reviewed-by: default avatarJeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 9a5e3fce

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+2 −4
Original line number Diff line number Diff line
@@ -1507,7 +1507,7 @@ static int dpu_encoder_helper_wait_event_timeout( 
	return rc;

}



void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)

static void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc)

{

	struct dpu_encoder_virt *dpu_enc;

	struct dpu_hw_ctl *ctl;
@@ -1803,9 +1803,7 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc, 
	if (needs_hw_reset) {

		trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));

		for (i = 0; i < dpu_enc->num_phys_encs; i++) {

			phys = dpu_enc->phys_encs[i];

			if (phys && phys->ops.hw_reset)

				phys->ops.hw_reset(phys);

			dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);

		}

	}

}

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

+0 −12
Original line number Diff line number Diff line
@@ -114,8 +114,6 @@ struct dpu_encoder_virt_ops { 
 * @handle_post_kickoff:	Do any work necessary post-kickoff work

 * @trigger_start:		Process start event on physical encoder

 * @needs_single_flush:		Whether encoder slaves need to be flushed

 * @hw_reset:			Issue HW recovery such as CTL reset and clear

 *				DPU_ENC_ERR_NEEDS_HW_RESET state

 * @irq_control:		Handler to enable/disable all the encoder IRQs

 * @prepare_idle_pc:		phys encoder can update the vsync_enable status

 *                              on idle power collapse prepare
@@ -151,7 +149,6 @@ struct dpu_encoder_phys_ops { 
	void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);

	void (*trigger_start)(struct dpu_encoder_phys *phys_enc);

	bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);

	void (*hw_reset)(struct dpu_encoder_phys *phys_enc);

	void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);

	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);

	void (*restore)(struct dpu_encoder_phys *phys);
@@ -342,15 +339,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( 
 */

void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);



/**

 * dpu_encoder_helper_hw_reset - issue ctl hw reset

 *	This helper function may be optionally specified by physical

 *	encoders if they require ctl hw reset. If state is currently

 *	DPU_ENC_ERR_NEEDS_HW_RESET, it is set back to DPU_ENC_ENABLED.

 * @phys_enc: Pointer to physical encoder structure

 */

void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc);



static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(

		struct dpu_encoder_phys *phys_enc)

{

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

+0 −1
Original line number Diff line number Diff line
@@ -776,7 +776,6 @@ static void dpu_encoder_phys_cmd_init_ops( 
	ops->wait_for_vblank = dpu_encoder_phys_cmd_wait_for_vblank;

	ops->trigger_start = dpu_encoder_phys_cmd_trigger_start;

	ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;

	ops->hw_reset = dpu_encoder_helper_hw_reset;

	ops->irq_control = dpu_encoder_phys_cmd_irq_control;

	ops->restore = dpu_encoder_phys_cmd_enable_helper;

	ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

+0 −1
Original line number Diff line number Diff line
@@ -766,7 +766,6 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) 
	ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff;

	ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff;

	ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush;

	ops->hw_reset = dpu_encoder_helper_hw_reset;

	ops->get_line_count = dpu_encoder_phys_vid_get_line_count;

}

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